Embedded Systems Design - March 2008 - (Page 43)

0308esd.p41to46 2/13/08 8:03 PM Page 43 Listing 1 is a complete HDL pro(p16r8) contains only eight register gram to generate a PLD for controlling bits, and there are 10 states in the systhe traffic lights at an intersection. tem. Written in ABEL’s state-machine forIt’s not difficult to reduce the mat, the listing illustrates the main number of states used by the trafficfeatures of PLD HDLs. light controller to eight. The four regThe first paragraphs contain the ister bits used in the four-stage delay header information—device naming, can be reduced to two register bits by device type, pin declarations, and inbuilding a simple two-bit counter. clude files. These are followed by a Listing 2 shows how this can be done macro that forces the program into a and presents the other two HDL strucknown state when a RESET signal is tures supported by ABEL: truth tables applied. Though not absolutely necesand Boolean equations. sary, this feature assists with power-up Truth tables are the most intuitive and test situations. And it’s free; since way to capture a function such as the there are unused pins on the chip, we one we seek and are particularly suitmight as well use one for initialization. able for describing complex bus deOther pins could be used as sensor incoding and encoding properties. ABEL puts to switch the traffic light only also supports vector signal descripwhen a car is tions to perwaiting at a mit bus modRecent innovations in red light. eling. PLD development system The state Listing 2a descriptions shows how technology are moving cycle the traftwo register PLD design back into the fic lights in bits are software realm. an obvious stepped manner. The through the last state description uses a compiler binary sequence {0, 0}, {0, 1}, {1, 0}, {1, 1} to create a four-stage directive to generate four identical counter. Listing 2b illustrates an states that are stepped through seequivalent truth table reduced to a quentially to create a four-clock-peripair of Boolean equations. The equaod delay. tions may be further reduced to a pair of shorter equivalencies as shown in OTHER HDL STRUCTURES When the description is entered, ABEL Listing 2c. The same function may also be described in a state machine in a compiles the HDL into the target PLD somewhat lengthier manner (Listing architecture and automatically gener2d). ates a test vector file for the part. BeState-machine, truth-table, and cause ABEL is linked to a full-logic Boolean descriptions in ABEL can be simulation system called DASH, the intermixed with schematic descripentire hardware configuration can be tions. This flexibility allows the provalidated in the same design environment. The generated fusemap files that grammer and hardware designer to work in the design description mediare used to program the PLDs are also um most suited to the task at hand. in a standard format, JEDEC, that can ABEL is supplied by Data I/O be used by many other CAE systems. (Seattle, Wash.), the leading vendor of For example, Logic Automation device programmers. Data I/O also (Beaverton, Ore.) provides software supplies DASH for schematic capture that turns JEDEC files into behavioral and simulation and PLDtest for automodels. matic test-pattern generation. If we tried to compile Listing 1 as it stands, we would get at least one erSWITCHING ENVIRONMENTS ror message. The PLD architecture HDLs are similar to general-purpose we’ve specified in the header field DesignContest Over $15,000 in cash prizes! Show off your design skills! Design a Windows® application using HEW Target Server (HTS). See how your designs function before you design them With HTS, you can see how your hardware/software will function while you're still in the design process, providing valuable real-time feedback. You can create helper applications, test benches and virtual control panels; automate processes and programming; and communicate with target MCUs/MPUs. *quantities limited Enter today for your chance at fun, fame and cash, and to receive a free HTS demo kit.* www.RenesasInteractive.com/ HTScontest2008 ©2008 Renesas Technology America, Inc. Renesas Technology America, Inc. is a wholly owned subsidiary of Renesas Technology Corp. All trademarks are the property of their owners. www.embedded.com | embedded systems design | MARCH 2008 43 http://www.RenesasInteractive.com/HTScontest2008 http://www.RenesasInteractive.com/HTScontest2008 http://www.embedded.com

Table of Contents Feed for the Digital Edition of Embedded Systems Design - March 2008

Embedded Systems Design - March 2008 Contents #Include Programming Pointers Designing DSP-based Motor Control Using Fuzzy Logic Hardware/Software Verification Enters the Atomic Age Efficient CRC Calculation with Minimal Memory Footprint Programming Your Own Microcontroller Advertising Index Break Points Marketplace

Embedded Systems Design - March 2008

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