Embedded Systems Design - June 2008 - (Page 26)

cover feature resented by the virtual platform typiFor example, if a block of logic is performed on the individual logical cally dictates what type of interface is only ever accessed by logic that runs at blocks inside of the hardware module. required. 50 MHz, there is no need to constantly The optimizations range from simple A virtual prototype that is comrecalculate that logic based on the 250algorithms, such as removing dead posed of cycle-accurate components MHz logic that may feed into it. These logic and constant propagation, to execution sequences are ﬁnally mapped will likely need only a simple adapter more complicated approaches such as to map the pins of the hardware object into code streams, which can be comduplicate-logic detection and replaceinto the data-types ment of certain logical opused by the platform, erations with more efficient equivalents. A model compiler can often take advantage while virtual prototypes written at higher Once each of the blocks of its knowledge of the logic to levels of abstraction has been subjected to local automatically generate the wrapper code will typically require a optimizations the compiler transactor to map syslogically elaborates the enand transactors necessary to link the tem-level transactions tire module. This elaborahardware object into the overall system. into the multiple clock tion phase exposes numercycles of pin transious additional optimization tions necessary to model this behavior piled into a single linkable object ﬁle. opportunities as the same algorithms in hardware. The hardware object itself is really that were applied to the individual logA model compiler can often take only a part of what is needed by to creic blocks are now applied to the modadvantage of its knowledge of the logic ate a useful virtual model. The object ule as a whole. After the logic has been contained in the design to automatitypically requires an integration layer completely optimized, it’s scheduled cally generate the wrapper code and to map its RTL-derived interface into into a set of execution sequences detransactors necessary to link the hardone which is needed by the virtual pending upon when it’s needed by ware object into the overall system and platform. The level of abstraction rephardware system. create a complete virtual model. This approach can be leveraged to target the same hardware object into multiple virtual prototypes at varying levels of abstraction depending upon the needs of user. HOW FAST WILL IT RUN? Once the virtual platform is assembled, the ultimate question is how fast will it run. The answer depends upon the level of accuracy of the models that comprise the platform. A platform consisting entirely of abstract models will execute quickly— sometimes faster than the real system—and allow for most high-level applications to be rapidly developed and debugged. Unfortunately, abstract models don’t have sufficient hardware detail to allow lower-level software such as firmware and drivers to be fully developed and debugged. On the other end of the spectrum is a virtual platform constructed entirely from the hardware implementation model. The entire hardware description is simulated in conjunction with the system software. This has the implementation-level detail necessary 26 JUNE 2008 | embedded systems design | www.embedded.com http://www.smxrtos.com/processors http://www.smxrtos.com/processors http://www.smxrtos.com/eval http://www.smxrtos.com/demo http://www.embedded.com

Table of Contents Feed for the Digital Edition of Embedded Systems Design - June 2008

Embedded Systems Design - June 2008 Contents #Include Party Bit Programmer's Toolbox Cover Feature: Virtual Hardware Platforms for Embedded Software Validation Allocating Memory in MATLAB-to-C Code MDD and IDEs: Making the Twain Meet in Embedded Systems Design Avoid a Thrashing Guest Editor Advertising Index Break Points Marketplace

Embedded Systems Design - June 2008

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