Embedded Systems Design - June 2008 - (Page 27)

cover feature to develop all of the software, but it will execute far too slowly to be of use for all but the most patient software engineer. An alternate approach combines the best aspects of both approaches. A hybrid virtual prototype combines the speed and versatility of the completely abstract model with the hardware accuracy of the implementation-level model. In a hybrid virtual prototype, the processing elements are typically represented using an instruction-set simulator (ISS). An ISS will typically execute the same binary executable as the real processor but will do so in a completely virtual manner. The remaining components in the hybrid virtual prototype are modeled at the abstraction level that best meets the goals of the software developer. In Figure 2, the memory subsystem is modeled in an abstract manner that enables the overall system to execute as quickly as possible but at the expense of cycle-level accuracy. The remaining components in the system were generated automatically from the RTL description. This combination maximizes the execution speed of the overall system but still delivers hardware accuracy for the components being addressed by the software. A hybrid virtual prototype can be constructed and reconfigured to meet the needs of the various constituent players in the validation lifecycle. Early in the design cycle of a system, the architect will typically require cycle-accurate components to make design decisions and perform design tradeoffs. At this stage, the virtual prototype may use a cycle-accurate ISS for the processor and an automatically generated model of the memory controller in order to ensure that the latency and throughput requirements for memory accesses are being met. As the design firms and software engineers begin using the virtual prototype for software development, the cycle-accurate ISS and memory controller may be swapped out for less accurate but higher speed implementations. Hybrid virtual prototype block diagram. ISS model Abstract model CPU Memory controller USB Generated model Interconnect fabric LCD Graphics controller Audio codec Figure 2 Other components in the system may be modeled at a high level of abstraction to deliver the fastest execution speeds or be represented using automatically generated models to deliver the greatest accuracy. In many cases, abstract models and automatically generated models for the same component can be interchanged to enable a virtual prototype to repre- Software Development Tools The Leader in Microcontroller Development Solutions C/C++ Development Kit including best-in-class compilers, genuine Keil μVision®, and royalty-free RTX RTOS. ULINK®2 Adapter for target debugging and Flash programming. ARM www.keil.com/arm A/D I/O Ports RunControl Debug Channel Flash ROM Timers Interrupts Cx51 www.keil.com/c51 PWM UART 2 CPU RAM RTC DMA C166 www.keil.com/c166 Out-of-the box support for more than 1,400 Microcontroller devices. I C/SPI Ethernet SD USB CAN Keil RTOS and Middleware components are specifically optimized for embedded systems and include TCP/IP, Flash File system, USB and CAN support. Call 1-800-348-8051 for a free demo CD. www.keil.com 27 www.embedded.com | embedded systems design | JUNE 2008 http://www.keil.com http://www.keil.com/arm http://www.keil.com/c51 http://www.keil.com/c166 http://www.keil.com http://www.embedded.com

Table of Contents Feed for the Digital Edition of Embedded Systems Design - June 2008

Embedded Systems Design - June 2008 Contents #Include Party Bit Programmer's Toolbox Cover Feature: Virtual Hardware Platforms for Embedded Software Validation Allocating Memory in MATLAB-to-C Code MDD and IDEs: Making the Twain Meet in Embedded Systems Design Avoid a Thrashing Guest Editor Advertising Index Break Points Marketplace

Embedded Systems Design - June 2008

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