Embedded Systems Design - June 2008 - (Page 45)

20 years ago The following “At the Bench” column ﬁrst appeared in the June 1989 issue of Embedded Systems Programming magazine. Thrashing BY ERNEST MEYER Avoiding a The topic of virtual memory and its interface with caches is important to programmers working with multitasking systems. The way hardware implements virtual memory addresses can have a drastic impact on code performance. his is the second in a series of columns on how hardware architectures inﬂuence software performance. Last month (Editor’s Note: 20 years ago), we examined two trade-offs in cache structures: write-through versus write-back and direct-mapped versus associative. This month we look at virtual memory and its interface with caches. This topic is particularly important to programmers working with multitasking systems. The way the hardware implements virtual memory addresses can drastically impact code performance. Virtual memory allows the program to use a larger addressing space than is offered by the actual bit width of a processor. A processor with a 16-bit-wide address bus (for example, the Z80) can directly access two 16-memory addresses. A virtual memory system is typically employed when the same processor accesses a larger range of addresses, typically 232 or about 2,000 Mbytes. Obviously, this is a larger addressing range than most people need. However, with virtual addressing this large space can be put to good use. One common way to realize a large addressing space is segmentation, which translates the logical address generated by a program into a linear address by adding it to a segment offset. Here, however, we’ll examine a more sophisticated virtual-memory mechanism called paging. Paging is used to translate a linear address into a physical address. Some systems don’t use paging but do use segmentation, in which case the linear address generated by adding a segment offset to a logical address is equivalent to a physical address. Some systems use paging but not segmentation, in which case the linear address is the same as the logical address generated by the program. Whether or not segmentation is employed or the linear address is the same as the logical address, paging translates the linear address into a physical address by adding an offset to the linear address. The offset T www.embedded.com | embedded systems design | JUNE 2008 45 http://www.embedded.com

Table of Contents Feed for the Digital Edition of Embedded Systems Design - June 2008

Embedded Systems Design - June 2008 Contents #Include Party Bit Programmer's Toolbox Cover Feature: Virtual Hardware Platforms for Embedded Software Validation Allocating Memory in MATLAB-to-C Code MDD and IDEs: Making the Twain Meet in Embedded Systems Design Avoid a Thrashing Guest Editor Advertising Index Break Points Marketplace

Embedded Systems Design - June 2008

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