Embedded Systems Design - June 2008 - (Page 46)

20 years ago look again in the page-table directory, calculate the offset in the indexed page table, look up the page-table entry, and calculate the physical address by adding the linear address and page-table entry. The processor then replaces an older TLB entry with the newly accessed page-table entry, on the assumption HIERARCHY OF OFFSETS that the page will be That may seem a little conused again very soon, fusing, so let’s look at it from and continues on its another perspective. Figure 1 The use of a triple-tier hierarchy way. All this activity shows a typical paging sys(three adds and two tem (the one used by the (root register, page-table directory, and memory reads before 80386). The program generpage table) allows a great deal of reaching the physical ates a 32-bit linear address programming ﬂexibility. address) obviously redivided into three parts: a disults in some performrectory index, a page-table ance degradation. In reference, and a page offset. normal operation, The upper 10 bits of the 32TLBs yield about a 98% hit rate. The hit it involves separate table lookups in the bit linear address, the directory index, rate usually decreases most signiﬁcantly directory and the page table to ﬁnd the are added to the page-table directory when tasks use deeply nested proceright physical address. If the page-table base in the root register. The page-table dures. This is because of the way the directory and all the page tables are directory entry contains the address of processor decides what page-table entry a page table. The next 10 bits of the lin- kept in main memory, the processor to discard from the TLB when there’s a needs to make two separate memory ear address are then added to the pagemiss. accesses to ﬁnd the byte. To reduce the table address to ﬁnd the required page reference in the table. Finally, the last 12 overhead of directory and page-table CACHE SCHEMING lookups, some processors use a translabits of the 32-bit linear address are tion look-aside buffer. A TLB is a cache, The two main cache-replacement added to an entry in the page table to schemes are the least frequently used usually fully associative, that’s used to ﬁnd the actual physical address. (LFU) and least recently used (LRU) hold active page-table entries. The The use of a triple-tier hierarchy 80386, for example, uses a 32-word, ful- algorithms. From the programmer’s (root register, page-table directory, and point of view, the LFU algorithm is ly associative TLB. page table) allows a great deal of proWhen a page-table entry is found in more elegant. An occasional reference gramming ﬂexibility. Multitasking systo some system variable in a distant an on-chip TLB (a TLB hit), the pagetems usually load a different value into and rarely used page, for example, has table lookup doesn’t normally add to the root register for each process, proa low cache life expectancy with LFU the address translation time. When a viding isolation between individual replacement. TLB miss occurs, the processor must tasks. At the same time, since the pageis found in a page-table entry, which is found by an indexed offset in a pagetable directory. The base of the pagetable directory itself is directly addressed by an on-chip control register, called a root register. table directory can point to different page tables, several processes can share common-area page tables for protected functions such as ROM. The page tables themselves allow a program to store and access sequential data and instructions in different physical locations. Sadly, this process is quite complex; The hierarchical steps used by the 80386 to generate an address in paged mode. 31 Directory 22 Table 12 Offset 0 + 31 CR0 CR1 CR2 CR3 Root Control registers Figure 1 JUNE 2008 | embedded systems design | www.embedded.com Directory base Directory + Page table base Page table 0 31 0 + Address Page base 46 http://www.embedded.com

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Embedded Systems Design - June 2008 Contents #Include Party Bit Programmer's Toolbox Cover Feature: Virtual Hardware Platforms for Embedded Software Validation Allocating Memory in MATLAB-to-C Code MDD and IDEs: Making the Twain Meet in Embedded Systems Design Avoid a Thrashing Guest Editor Advertising Index Break Points Marketplace

Embedded Systems Design - June 2008

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