Embedded Systems Design - August 2008 - (Page 32)

0808esd.p30to33 7/21/08 10:37 AM Page 32 feature A coherent processing system. CPU0 L1 Cache OCP L1 Snoop tags CPU1 L1 Cache OCP Snoop port L1 Snoop tags CPU2 L1 Cache OCP Snoop port L1 Snoop tags CPU3 L1 Cache OCP Snoop port Snoop port OCP IOCU port OCP Memory interface unit OCP L2 Cache Figure 1 L1 Snoop tags Global interrupt controller OCP Request unit Snoop agent Response unit coherence-message communication to each processing element as depicted in Figure 1 in a system MIPS calls a Coherent Processing System (CPS). This system provides the means of snoop-type cache coherence. Coherence messages embody a new type of command within the OCP protocol. Members of the processor system send coherence messages toward a centralized coherence manager that provides access ordering (serialization) and message routing to provide snoop-type access to peer members. These peers will respond with their individual L1-line status and post a message response. Depending on responses, the coherence manager initiates data movement for coherent data among cores and funnels access toward higher-level memory hierarchies such as L2 and L3 caches. I/O coherence units also provide a means to phase-in/out data toward/from the coherent address space and are part of coherent-message exchange. In addition to new message-type commands within the OCP protocol, individual processors are required to respond to coherent status requests and are therefore not solely initiators (masters) of bus transactions. The CPS might address this requirement by providing an OCP slave port to receive and respond to messages initiated by the coherence manager. Coherent requests by a processor will use the OCP master port. Within the processing cluster, coher32 ence-message exchanges between cores and the coherence manager are dubbed interventions. OCP slave ports of processors receiving interventions are therefore intervention ports. As depicted in Figure 1, each individual processor of the MIPS 1004K system is based on our multithreaded processor architecture, providing two independent threads and processing context within the envelope of a singlescalar, 9-stage pipeline. Level 1 data-cache tag arrays are duplicated to be accessible simultaneously for CPU operation and intervention lookup. MESIstyle cache-line coherency is supported. The coherence manager of the processing system receives and serializes incoming messages through its request unit—OCP slave ports, driven by each CPU and I/O-coherence units. Serialized messages are routed depending on their address space and context either to higher-level cache hierarchies using the memory interface unit, or toward processor peers and I/O-coherence units using the snoop agent. The snoop agent initiates OCP master transactions (interventions) to look up the coherent L1 cache-line status for each processor. Interventions returned to the initiator of a message, called self-interventions, allow the initiator to provide access ordering. Responses to coherent messages initiated by CPUs as well as data responses are formulated within the response unit and routed to individual CPUs. COHERENT OCP COMMANDS OCP commands used within the 1004K CPS can be classiﬁed into three categories: • • • Coherent messages maintain a MESIstyle cache-line status. These messages are a result of CPU load and store operations and can initiate data movement between CPUs and the memory subsystem. All peer CPUs of the CPS will receive coherent messages posted by an initiator and respond according to their cache-line coherent state. The coherence manager will initiate data movement as required. Coherent cache-manipulation commands are used for cache-line maintenance within the coherent address space. I/O trafﬁc will bring new coherent lines into the domain or remove coherent context from cache lines. Further, operations that synchronize memory hierarchy are performed. Noncoherent commands perform OCP main-port transactions on memory regions outside the coherent address space. These represent OCP read and write commands. COHERENT MESSAGES The CPS may implement four coherent messages that are caused by L1 cacheline-status changes due to CPU load and store activity. The initiating CPU sends AUGUST 2008 | embedded systems design | www.embedded.com http://www.embedded.com

Table of Contents Feed for the Digital Edition of Embedded Systems Design - August 2008

Embedded Systems Design - August 2008 Contents Number Include Parity Bit Programmer's Toolbox Cover Feature: Virtualization for Embedded X86 Multiprocessor Applications Wanted: Industry Standards for Benchmarking Embedded VMM Hypervisors Achieving Cache Coherence in a MIPS32 Multicore Design Memory Allocation in C Advertising Index Break Points Marketplace

Embedded Systems Design - August 2008

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