Embedded Systems Design - August 2008 - (Page 33)

0808esd.p30to33 7/17/08 11:55 AM Page 33 7” Touch Panel Computer for embedded GUI / HMI applications this message as an OCP master-port command. Peer CPUs of the system receive interventions based on this linestatus change and will respond with their local cache-line status. The ﬁrst message type is the CohReadOwn, denoting a cache miss that occurred through an attempt to modify a cache line. As Figure 2 shows, peer cores encountering this line in status “Modiﬁed” will force a write-back into the memory subsystem and perform a local invalidate. As an optimization, locally encountered line data will be forwarded to the requester CPU to reduce access latency. The requester CPU will install this line as “Exclusive” and perform the line-modifying instruction. Then the cache-line status will change to “Modiﬁed.” While waiting for line reﬁll, the requester CPU will continue execution of another thread. The CohReadShared message indicates that a cache miss occurred through a line read operation. No line modiﬁcation is intended. As Figure 3 shows, peer cores encountering this line in status “Modiﬁed” will force a write-back into the memory subsystem. Hitting peer lines will migrate to “Shared” status. Hit data is forwarded to the requester core and installed in state “Shared.” Then the line read operation is performed. While waiting for line reﬁll, the requester CPU will continue execution of another thread. CohUpgrade indicates that a linemodifying instruction encountered a cache hit on a “Shared” line. As Figure 4 shows, peer cores will be notiﬁed to invalidate hitting lines. The “Shared” line is then upgraded to “Modiﬁed” after the modifying instruction is executed. Finally, the CohWriteBack message signiﬁes eviction of a coherent cache line. The coherence manager will initiate data movement through the intervention port and forward data to the memory subsystem. The evicted cache line is then replaced by a new—possibly coherent— address. In this case, a CohReadOwn or CohReadShared has caused the eviction. COHERENT CACHE MANIPULATION COMMANDS In response to cache manipulations, co- quantity 1 pricing starts at 449 Powered by a 200 MHz ARM9 CPU Low power, Industrial Quality Design Mountable aluminum frame 64-128MB DDR RAM 512MB Flash w/ Debian Linux Programmable FPGA - 5K LUT 7” Color TFT-LCD Touch-Screen 800x480 customizable video core Dedicated framebuffer - 8MB RAM Audio codec with speaker Boots Linux 2.6 in about 1 second Unbrickable, boots from SD or NAND Runs X Windows GUI applications An example of coherent read own messaging (CohReadOwn). Core DCache Core0 D$$ Invalid Store Miss OC_MCmd OC_SResp IV_MCmd IV_SResp Lookup core 1,2,3 Invalid Core0 D$$ Exclusive Fill Store cohReadOwn SResp cohReadOwn OK Core0 D$$ Modified Runs Eclipse IDE out-of-the-box Our engineers can customize for your LCD Over 20 years in business Never discontinued a product Engineers on Tech Support Open Source Vision Custom configurations and designs w/ excellent pricing and turn-around time Most products ship next day Other DCaches Interv. port Main port L2 Main port L2_MCmd L2_SData Core initiated Miss Read Fill DATA Coh. manager Core initiated See our website for our complete product line CPU 0 encounters a store miss and initiates a cohReadOwn (intent to modify) message toward the coherence manager. The coherence manager sends interventions toward all cores. None of the peers have this cache line available, and an OCP read request is directed toward the L2 cache. Returning data will be installed with the coherence attribute “Exclusive” at the requester core. After the store operation completes, the cache line status migrates to “Modified.” Figure 2 Technologic SYSTEMS We use our stuff. visit our TS-7800 powered website at www.embeddedARM.com (480) 837-5200 http://www.embeddedARM.com http://www.embeddedARM.com

Table of Contents Feed for the Digital Edition of Embedded Systems Design - August 2008

Embedded Systems Design - August 2008 Contents Number Include Parity Bit Programmer's Toolbox Cover Feature: Virtualization for Embedded X86 Multiprocessor Applications Wanted: Industry Standards for Benchmarking Embedded VMM Hypervisors Achieving Cache Coherence in a MIPS32 Multicore Design Memory Allocation in C Advertising Index Break Points Marketplace

Embedded Systems Design - August 2008

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