Embedded Systems Design - August 2008 - (Page 34)

0808esd.p30to33 7/17/08 11:55 AM Page 34 feature An example of coherent read shared messaging [CohReadShared). Core DCache Core0 D$$ Invalid Load Miss OC_MCmd OC_SResp IV_MCmd IV_SResp IV_SDATA Core0 D$$ Shared Fill Load cohReadShared SResp cohReadShared DVA Lookup core WR DATA 1,2,3 Modified Shared Core0 D$$ Shared An example of coherent upgrade messaging (CohUpgrade). Core DCache Core0 D$$ Shared Store Hit OC_MCmd OC_SResp IV_MCmd IV_SResp Lookup core 1,2,3 Shared Core0 D$$ Exclusive Core0 D$$ Modified Store cohUpgrade OK cohUgrade OK Main port Interv. port Other DCaches Interv. port Main port Other DCaches Invalid L2 Main port Write WR DATA Coh. manager Core initiated L2 Main port L2_MCmd L2_SData Core initiated Hit L2_MCmd L2_SData Core initiated Hit Coh. manager Core initiated CPU0 encounters a load miss on a coherent cache line and initiates a cohReadShared message (no intent to modify). The coherence manager sends interventions to all cores where Core 1 responds with a hit—”Modified.” The coherence manager now initiates a write-back of the modified line and moves line data from Core 1’s intervention port to the memory subsystem. The hitting Core 1 cache line migrates to “Shared” status. Line data movement also forwards to Core 0 where it is installed in the “Shared” state. Core 0 encounters a store hit on a “Shared” marked cache line. A cohUpgrade request is sent and the coherence manager initiates interventions to all cores. Core 1 responds with a hit “Shared” and invalidates its line. Core 0 is permitted to upgrade its cache line to “Exclusive.” After the store has completed, the cache line status migrates to “Modified.” State “Exclusive” is required (rather than “Modified” immediately) since between intervention response and store execution, other cores could intervene and force a modified write-back—migrating to “Shared” without awaiting the Core 0 store. Figure 3 Figure 4 herence messages are initiated and sent to peers. CohCopyBack—write back a coherent cache line to the memory subsystem. Cache-line hits in state “Modiﬁed” will be written back. Line status migrates to “Shared.” CopyBack data movement will be initiated by the coherence manager using the intervention port. CohInvalidate—purge a coherent cache line without writing back its contents to the memory subsystem. This command is always data-less and is posted to each peer of the CPS. Invalidate-type cache operations cause a CohInvalidate message. CohWriteInvalidate—an I/O coherence unit injects a new cache line into the coherent domain. Existing peer line data will be invalidated throughout the CPS. CohReadInvalidate—an I/O coherence unit notiﬁes the system about a cache line leaving the coherent domain. Existing peer line data will be invalidated throughout the CPS. CohCompletionSync—data-less 34 command to maintain ordering. Local buffers of CPS peers are ﬂushed towards the memory subsystem. The CPUSYNC instruction causes the CohCompletion-Sync for CPUs attending the coherent domain. SYNC command arguments (sync types) help control the depth of ﬂush operations throughout memory hierarchies. The CPS reserves certain argument encodings to support low-overhead access ordering. NONCOHERENT COMMANDS Traditional OCP commands such as “Read” and “Write” are supported throughout the CPS to handle data access for noncoherent memory access. The Read command is issued when a miss within a cached, noncoherent address or an uncached access causes a read operation from the memory subsystem. Response data—if cacheable— will be installed as noncoherent, whereas uncached data are consumed directly. Fetch as well as load and store activity causes Read transactions. The Write command is issued when cached, noncoherent eviction data or un- cached-address-range stores will be written back to the memory subsystem. The OCP main port of a core performs the command and data phases of the transaction. OCP WORKS WELL FOR CPS The OCP interconnect lent itself well to support message-based coherence implementations. A centralized coherence manager serializes coherence messages emanating from an individual core and inquires about the coherence status of peer cores. Data forwarding between cores decreases access latency and reduces trafﬁc to higher levels of memory hierarchy. Individual cores possess an OCP master port to initiate data access and an OCP slave port to receive inquiries from the coherence manager. ■ Matthias Knoth, a design engineer for MIPS Technologies, Inc., is responsible for low-power microarchitecture and 1004K processor implementation. Knoth has more than 13 years experience in the semiconductor industry and holds a masters in electronics from the University of Technology, Chemnitz, Germany. You may reach him at knoth@mips.com. AUGUST 2008 | embedded systems design | www.embedded.com http://www.embedded.com

Table of Contents Feed for the Digital Edition of Embedded Systems Design - August 2008

Embedded Systems Design - August 2008 Contents Number Include Parity Bit Programmer's Toolbox Cover Feature: Virtualization for Embedded X86 Multiprocessor Applications Wanted: Industry Standards for Benchmarking Embedded VMM Hypervisors Achieving Cache Coherence in a MIPS32 Multicore Design Memory Allocation in C Advertising Index Break Points Marketplace

Embedded Systems Design - August 2008

For optimal viewing of this digital publication, please enable JavaScript and then refresh the page. If you would like to try to load the digital publication without using Flash Player detection, please click here.