Microwave Engineering Europe - March 2008 - (Page 28)

28 EDA — CIRCUIT EXTRACTION Figure 6: iNets for a very simple RLC circuit, showing immense detail in 3D for manufacturing. simple short circuit interconnect in the electrical schematic diagram and then in the layout, route that interconnect with the internal knowledge of the technology being used. For example, on a four-layer PCB, the ﬁve possible locations of the track along with the customer-speciﬁc via hole options are offered during the routing process. These are all design rule check (DRC) correct against the given technology (gallium arsenide [GaAs], LTCC, Duroid, printed circuit board [PCB], silicon [Si], and silicon germanium [SiGe]) and result in a manufacturable interconnect in the layout world. Using ACE technology, this physical layout can now produce an advanced netlist, which, when combined with the schematic electrical design of real components, provides incredibly accurate simulation results. The RLC schematic in Figure 6 shows iNets on a simple design. The graph shows the expected RLC response of the grey trace when the ACE extraction is disabled, and the ripple and loss in blue as expected from the long meandered iNets drawn in the layout. These iNets, viewed in 3D, show that the immense detail required for manufacture can easily be produced with an appropriate technology ﬁle, and a few mouse clicks to route the interconnect. Example 2 – MMIC spiral coupling Making use of iNets coupled with ACE extraction technology, the design cycle for complex microwave designs is reduced from hours to minutes. Two identical designs, shown in Figure 7, have close to identical layout — trace-chamfered corners being the major difference. Explicit microwave circuit element design has now been replaced with the much simpler RF approach in terms of schematic circuit-level entry coupled with iNets technology producing an identical layout. Once extracted through ACE, the simulation results are incredibly similar as per Figure 8, but with the beneﬁt of a hugely reduced design time. ACE can be pushed even further with designs that now include previously un-simulated reactions. In the same single-stage ampliﬁer design a second spiral inductor is added into the schematic diagram using iNets, which is completely isolated from the original circuit in the electrical schematic. With ACE extraction, as shown in Figure 9, cross-coupling due to the physical layout and spiral proximity now perturbs the original simulation results, enabling the Figure 7: Identical circuits with very similar layout — one taking minutes, the other hours. Figure 8: Simulation accuracy using traditional design versus ACE extraction. Microwave Engineering Europe ● March 2008 ● www.mwee.com 024_025-026-028-029_030_MWEE.ind28 28 21/02/08 11:09:13 http://www.mwee.com

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Microwave Engineering Europe - March 2008 News Contents Comment Wireless Infrastructure: A Direct Conversion I/Q Demodulatordrives Favorable Basestation Cost-performance Metrics Wireless Infrastructure: Mobile World Set to Reshape the Internet RF Amplifiers: Latest Advances in RF Amplifiers Include a CMOS PA Operating at 77 GHz and Significant Advances in PAs for WiMAX and Broadband Applications Many Applications Still Require Unique Performance Benefits of BeO ACE Automated Circuit Extraction Returns to Real Design by Exploring Design Alternatives and Changes in Seconds Exceeding the Standard for Wireless Sensor Networks Products Calendar

Microwave Engineering Europe - March 2008

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