Microwave Engineering Europe - March 2008 - (Page 29)

EDA — CIRCUIT EXTRACTION 29 design engineer to ensure that this effect is accounted for during the very ﬁrst design cycle at the simulation stage, before costly prototyping. Example 3 –PCB Design In this ﬁnal example, ACE capabilities are applied to a complex, 16-layer PCB application early in the design ﬂow (shown in Figure 10) in order to efﬁciently and accurately design the RF transmit signal path on the top side of the board alongside digital control on the bottom side and ground planes in between layers. All in all, at this stage of the design, the 16-layer board has 168 nets and therefore 336 ports, dozens of vias — some blind, some buried and some though vias, and yet a simple schematic circuit with the routes being generated in the layout world. Analyzing this large a design with a 3D planar solver is a time-consuming task because of the time required to create the Green’s function for the multiple, nonuniform layers. 3D FEM techniques would also take a long time — even longer because of the amount of metal. Even 3D ﬁnitedifference time-domain (FDTD) software products would suffer due to the high port count. Using the ACE tool with this design provides an answer in a little over one minute when modeling all the coupled lines with the GMCLIN MoM models. In the extracted 3D view shown in Figure 11, the ACE tool decomposes parallel line segments into coupled-line models such that as nets that have some segment or trace become parallel or stop being parallel with other nets’ segments, the software inserts a new coupled-line model in series with the original, with the difference between the two representing one more or one fewer coupled lines. The ACE software is capable of creating very dense networks of interconnects in this way by ﬁnding units, or portions, of the layout that can be grouped together based on the extensive library of models in the AWR design environment. These are the very same models that designers have been relying upon for nearly a decade to design RF/microwave circuits up to and beyond 100 GHz. This coupling can be across the same layer, or through multiple layers, assuming they are not separated by a ground plane. The equivalent substrate deﬁnition is calculated depending on the board stack, and can be different in different areas of the board. Coupling can easily be seen in Figure 11, both across the same layer on the left and between layers towards the centre of the 3D view. Overlapping traces are modeled as capacitance, shown on the top right area of the 3D view. Finally, via hole modeling is chosen by the designer, and can be a simple resistance, an S-parameter ﬁle or a more complex AWR VIA schematic model. This design generates an equivalent netlist that is some 2000 nodes long, and is extracted and simulated in under 90 seconds. Real-time physical movement of lines, and resultant changes to the design are perfectly feasible. True EMI verﬁcation The same geometries that were sent to an EM solver in the past can now be sent to ACE software. Throughout the design ﬂow, the ACE tool can be used, in conjunction with EM-based discontinuity and coupled line models, to design and reﬁne. The very same geometries that are sent to ACE during design can then be sent for veriﬁcation, capacity permitting, to a variety of best-in-class third-party EM tools integrated into AWR’s software through the Figure 9: Cross coupling of a second spiral inductor, drawn as an iNet and the resulting change in simulation response. Figure 10: 16-layer PCB with 168 iNets interconnect extracted via ACE in 1 minutes 23 seconds on a 2-GHz Centrino Duo machine. Microwave Engineering ● March 2008 ● www.mwee.com 024_025-026-028-029_030_MWEE.ind29 29 21/02/08 11:09:25 http://www.mwee.com

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Microwave Engineering Europe - March 2008 News Contents Comment Wireless Infrastructure: A Direct Conversion I/Q Demodulatordrives Favorable Basestation Cost-performance Metrics Wireless Infrastructure: Mobile World Set to Reshape the Internet RF Amplifiers: Latest Advances in RF Amplifiers Include a CMOS PA Operating at 77 GHz and Significant Advances in PAs for WiMAX and Broadband Applications Many Applications Still Require Unique Performance Benefits of BeO ACE Automated Circuit Extraction Returns to Real Design by Exploring Design Alternatives and Changes in Seconds Exceeding the Standard for Wireless Sensor Networks Products Calendar

Microwave Engineering Europe - March 2008

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