Microwave Engineering Europe - June 2008 - (Page 13)

COVER FEATURE — HIGH SPEED LOGIC 13 Hittite’s 13 Gbps high speed logic family provides reduced jitter, programmable output voltage and lower power consumption By Michael E. Harrell and Jon R. Firth, Hittite Microwave Corporation ver the last few years, the transition from analog to digital RF technology has generated the need for high performance digital logic at higher data rates. The evolution of high speed digital communication has placed more emphasis on s-parameter measurements, the ability to measure lower jitter, and more widespread use of differential circuits to provide noise immunity. These new requirements demand high speed logic and control circuits with lower random and deterministic jitter speciﬁcations, lower propagation delay, reduced data skew values and lower power consumption. High speed logic is a key requirement in many wideband data acquisition systems, such as software deﬁned radio or real time digital radar. In these systems, the common design trend is to simplify the complexity of all of the stages from signal acquisition (the antenna) to analog-to-digital conversion (ADC), resulting in digitization of RF signals at higher sample rates. These higher data rates have caused more stringent requirements to be placed on the high speed interface and control logic devices. O To meet all of these requirements, Hittite Microwave has developed a family of 13 Gbps digital building blocks. The ﬁrst of these devices include the HMC670LC3C 1:2 Fanout Buffer, the HMC671LC3C XOR/XNOR gate, the HMC672LC3C AND/NAND/OR/NOR gate, and the HMC673LC3, D-Type Flip Flop (see table). These logic devices may be used individually, or in combination to implement many critical digital subsystems spanning a myriad of applications including broadband test equipment, ATE, military communications, radar, frequency synthesis, 10/100G Ethernet and SONET/SDH optical systems. The HMC670LC3C 1: 2 Fanout Buffer distributes precise clock or data signals in high performance applications. The device provides buffering capability for clock frequencies up to 13 GHz, and serial data transmission rates up to 13 Gbps. The Figure 1: In this typical example, a 12 Gbps serial data stream is retimed and demultiplexed. HMC670LC3C Fanout Buffer also provides very low data skew (< 2 ps) between data ports, which is ideal for critical time domain measurements since any skew between data ports may create race conditions. The HMC670LC3C is also ideal for bit-error-rate testing (BERT) applications since it helps designers to reduce the complexity of the clock distribution chain. The HMC670LC3C also exhibits fast rise and fall times of 20 ps and a propagation delay of 55 ps. The device exhibits less than 1 ps of deterministic jitter, less than 100 fs of random jitter, and typically dissipates 240 mW. The HMC671LC3C provides either an XOR or XNOR logic function. When conﬁgured as a XOR gate, the HMC671LC3C may be used to generate inverted data streams or may be used to implement a phase detector or a bit-error rate detector. The HMC671LC3C provides Microwave Engineering ● June 2008 ● www.mwee.com http://www.mwee.com

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Microwave Engineering Europe - June 2008 Contents Comment News Cover Feature Designing and Simulating a Wireless LAN Antenna 60GHz: Achieving the Ultimate Wireless Dream New Radar Developments Include HFETs to Challenge DMOS/LDMOS and a 77-GHz CMOS PA for Automotive Applications Testing Raises Concerns Over 802.11-Based High-Speed Bluetooth IP2 & IP3 Design Considerations with Direct Conversion I/Q Demodulator Receiver Products Calendar

Microwave Engineering Europe - June 2008

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