Microwave Engineering Europe - July/August 2008 - (Page 16)

16 CAD/EDA Software-Deﬁned Radio platforms The IMEC research center has demonstrated a large-scale design of a Software-Deﬁned Radio (SDR). By Bart Van Poucke, Bruno Bougrad, and Jan Provoost, IMEC. n the coming decade, SDRs will drive all types of wireless devices, answering the exploding demand for multi-standard, high-throughput wireless communication. Such SDRs will have rigorous constraints for energy consumption, real-time processing, low-cost fabrication, and short time-to-market design. They will be implemented on multi-purpose, multiprocessor System-on-Chips (MPSoCs). But the design of SDRs on MPSoCs brings about a dramatic increase in the complexity of hardware and software design. IMEC is an independent research center, focusing on next-generation chip technology and on the enabling technologies for ambient intelligence. IMEC’s research bridges the gap between fundamental research at universities and development in the industry. IMEC has its headquarters in Leuven (Belgium), and employs more than 1500 people, including 500 industrial residents and guest researchers. One of the research domains of IMEC concerns solving the technology bottlenecks for future wireless, multi-mode, multimedia devices. A team at IMEC recently took the design complexity hurdle. They designed and demonstrated an SDR on MPSoCs, using advanced methods such as electronic systemlevel (ESL) design and co-emulation. The team ﬁrst created a high-level virtual model of the SDR MPSoC. Then, each component of the platform was incrementally reﬁned to the RTL level, verifying each step through co-simulation and co-emulation. State-of-the-art processor design tools were used to further model one of the critical low-power processors of the MPSoC. Also with the ESL tools, the data transfers between the processing cores were optimized to meet the tight timing constraints of baseband processing. The ESL tools helped to achieve an efﬁcient design, especially through the architectural exploration and the early performance assessment. Designing SDR MPSoCs calls for ESL tools In general, an SDR is a reconﬁgurable and programmable hardware platform that can potentially tune to any frequency I band and receive any modulation. The SDR solution that IMEC envisions has a reconﬁgurable front-end combined with a (re)programmable baseband platform. It targets 802.11n, 802.16e, and 3GPP-LTE. Potentially, an SDR consumes much more energy than dedicated hardware solutions. To overcome this, a trade-off had to be made for each functional unit between hardware and software solutions, carefully weighting the resulting energy efﬁciency. Hardware abstractions could only be introduced when the impact on the overall energy consumption was low, or when the extra ﬂexibility could be exploited for improved energy management. These considerations naturally led to an MPSoC architecture in which the various tasks could be implemented on different cores, providing the necessary performance and ﬂexibility at a minimum cost. Traditionally, chips are designed close to the physical level. For MPSoCs, this will not do, as the physical design does not allow early veriﬁcation and tuning. ESL is a design approach that raises the abstraction to the highest level of the target platform. This allows starting with an early veriﬁcation of the hardware and software choices, long before a complete RTL model or a silicon prototype are available. Therefore, IMEC chose to use advanced ESL design methods. Another consideration was that commercial SDR MPSoCs will be designed under rigorous time-to-market, energy and real-time processing constraints, which will also call for ESL design tools. ESL allows high-level, selective abstraction The IMEC team ﬁrst created a virtual model of the target SDR platform. This is a transaction-level model (TLM), speciﬁed in SystemC. For each component, a suitable abstraction level was chosen, depending on the IP availability, the complexity, and the speed requirements for the simulation. A major plus of the tools used is that components deﬁned on different abstraction levels can still be co-simulated. This allows designing and reﬁning each component independently. With that early version of the virtual SDR ready, work was started on the hardwaredependent software. This software, including the hardware abstraction layer, enables basic simulated hardware/software validation. It also provides early feedback on the performance of the hardware/software choices and interaction. At this stage, this feedback could already be used to optimize the interconnect and the handling of interrupt events. In a next step, the development of the functional software was initiated. The programmable and non-programmable cores on the platform are either custom processing units modeled with Application Speciﬁc Integrated Processors (ASIP) development kits or third-party IPs, for example ARM Instruction Set Simulators (ISS). Each ISS is placed in a SystemC container with a bus interface. The ISS is simulated in the context of the SystemC platform simulation. In that way, multiple cores and their synchronization can be debugged concurrently. Platform exploration Throughout the design and reﬁnement of the virtual SDR platform, the model of the bus was kept at cycle accurate level. This bus offered a correct and welldeﬁned interface to attach units of various abstraction levels (for example peripherals). These units could then be veriﬁed and reﬁned, starting with a model of their functional behavior only. Later, exact timing information was added to match the real requirements. The next step, exploring the platform to optimize its performance, could then be performed independently from the rest of the platform development. Platform exploration consists of gradually identifying and repairing bottlenecks. Having a virtual model of the platform, the IMEC team could start platform exploration early in the design ﬂow. If they would have designed the SDR directly at the HDL level, it would have been much more difﬁcult and timeconsuming to evaluate changes in the interconnect- and platform-architecture, Microwave Engineering Europe ● Julay/August 2008 ● www.mwee.com http://www.mwee.com

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Microwave Engineering Europe - July/August 2008 Contents News Comment Cover Feature: Effective EM Simulations with Micro−λ Resolution in Macro-λ Objects — General Huygens Box Implementation RF CMOS: Programmable Transceiver IC Minimises OEM Inventory for Femtocells CAD/EDA: Software-Defined Radio Platforms CAD/EDA: Cadence Enhances RF Verification While AWR Delivers an Improved Microwave Office How to Meet the Design Challenges of WiMAX Power Amplifiers Products Calendar

Microwave Engineering Europe - July/August 2008

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