Microwave Engineering Europe - July/August 2008 - (Page 17)

CAD/EDA 17 and relate them to changes in the performance. To explore the platform, IMEC examined the performance based on simulating the real behavior of the selected IPs and bus connectivity. The interconnect architecture was optimized by introducing various bus architectures and progressively searching for the ideal conﬁgurations. The team assessed, for example, if a further segmentation of the interconnect would improve the performance, or on which interconnect segment a particular unit should be placed to get the best access time. At each step, the bus throughput and utilization was evaluated. And a simple software test bench was developed on the ARM ISS to do proﬁling and interconnect stress tests. The test bench emulates the interconnect requests at maximum load. Gradual RTL reﬁnement with co-simulation and co-emulation Gradually, and for each unit separately, IMEC reﬁned the design down to the RT level. The rest of the platform was kept at TLM level, serving as a test bench to verify the RTL units. In this co-simulation setup, the TLM platform simulator in SystemC was the master, calling the RTL simulator to simulate the units already at RT level. In this way, the TLM and RTL blocks could be co-simulated in the early stage of the RTL reﬁnement, when most components were still deﬁned as TLM. However, as more blocks were RTL speciﬁed, the speed of the co-simulations rapidly became a bottleneck, reducing the validation that could be achieved. To overcome this issue, the team then changed the test setup, employing co-emulation. Usually, RTL modules are veriﬁed with pure hardware emulation. However, this would require developing synthesizable RTL test benches. Co-emulation avoids this step. It is a new veriﬁcation technique in which SystemC TLM blocks are simulated on a PC, and the RTL blocks are simulated on a dedicated emulation station. The two simulation environments communicate via transactors. These transactors or communication pipes are implemented as function calls between the SystemC platform and the SystemVerilog direct programming interface of the RTL simulation. During a transaction, the simulation control is temporarily transferred from the emulator station to the SystemC environment on the PC. Simultaneously, the emulator hardware is stopped through clock gating. Next, the SystemC simulator executes the function called through the transactor. This function may, in turn, trigger events that start other processes or threads. When the original function ﬁnishes, the emulator station resumes functioning. As the emulator hardware clock was stopped during the transaction, the emulator sees the SystemC function returning immediately (the execution time is zero). Design of a low-power pre-synchronization ASIP In burst-based communication, for example in IEEE802.11 or IEEE802.16, the burst detection functions have high duty cycles. They thus need an ultra low power implementation; but at the same time they should still be programmable so that they can support various modes. For its SDR MPSoC, IMEC designed a dedicated lowpower pre-synchronization ASIP targeting the IEEE802.11a/n and IEEE802.16e synchronization at 20MHz input rate. The ASIP was implemented in three steps. First, the processor was modeled in LISA (Language for Instruction-Set Architecture). Then, RTL code was generated, synthesized and proﬁled in a gate level power simulation. Finally, a backend experiment was carried out to ensure timing closure. IMEC chose a tool set that enabled the generation of software development tools, such as an assembler, linker, and instruction-set simulator very early in the design process. The processor microarchitecture can then be co-optimized with the kernel software. Moreover, the tools offer strong support for platform integration (by generating a wrapper for SystemC-based virtual platform modeling) and good-quality automated RTL code generation. The resulting processor delivers a theoretical maximum performance of 5 GOPS (32 bit equivalent) at a peak power of 25 mW. The energy efﬁciency is thus 200 MOPS/mW (fully loaded). IEEE802.11a synchronization (20 MHz) requires only 630 MOPS. The processor consumes 7.17 mW when executing this kernel (79.5 MOPS/mW). The more demanding IEEE802.16e synchronization (20 MHz) requires 1838 MOPS. For this kernel the estimated average power is 15.86 mW (115.89 MOPS/mW). The achieved energy efﬁciency is 2 to 4 times higher than in typical SDR baseband processors. This ASIP is ready for low power packet detection, enabling energyaware MPSoC SDR platforms. ESL tools assisted in overcoming MPSoC design hurdles With the ESL tools from CoWare the IMEC team was able to overcome the complexity hurdles in designing an SDR on MPSoC. Designing the MPSoC in a more traditional way, closer to the hardware level, would have been prohibitively cost- and timeinefﬁcient. Throughout the development, IMEC used the CoWare Platform Architect and CoWare Processor Designer tool families extensively. The most notable advantages and efﬁciency gains came from the ability to build a virtual platform at an abstract level in SystemC. And the possibility to co-simulate and co-emulate units reﬁned at RT level in the context of the complete platform also proved to be a major plus. It enabled early veriﬁcation and trade-off of the hardware and software choices that had been made. It also allowed exploring architecture alternatives without having to build an RTL platform, or even a silicon prototype. Also the ability to proﬁle parameters on the virtual platform using bus transaction traces and analysis tools provided early feedback on the design. It especially allowed understanding the complex interactions between the various units of the MPSoC before a fully functional system was available. About the authors: Bart Van Poucke is a Technical Business Manager within IMEC. Bart is responsible for IMEC’s technical business relations in the ﬁeld of Nomadic Embedded Systems. Bart obtained his electrical engineering degree at the KIHO (Gent, Belgium) in 1996. He can be reached at: Bart. Vanpoucke@imec.be Bruno Bougard has been a researcher at IMEC since 2000. He has a an M. Sc. in Electrical Engineering from the Polytechnic University of Mons, Belgium (2000) and the Ph. D. in Electrical Engineering from the K.U.Leuven, Belgium (2006). Bruno can be reached at: Bruno.Bougard@imec.be Jan Provoost (Jan.Provoost@imec.be). is a scientiﬁc editor at IMEC, reporting about IMEC’s breakthroughs in international scientiﬁc magazines and newsletters. Jan has a Masters degree in Languages (1989) and a Masters degree in Information Science (1993), both from the K.U.Leuven, Belgium. He can be reached at: Jan. Provoost@imec.be Reprinted courtesy of EDA DesignLine Microwave Engineering ● July/August 2008 ● www.mwee.com http://www.mwee.com

Table of Contents Feed for the Digital Edition of Microwave Engineering Europe - July/August 2008

Microwave Engineering Europe - July/August 2008 Contents News Comment Cover Feature: Effective EM Simulations with Micro−λ Resolution in Macro-λ Objects — General Huygens Box Implementation RF CMOS: Programmable Transceiver IC Minimises OEM Inventory for Femtocells CAD/EDA: Software-Defined Radio Platforms CAD/EDA: Cadence Enhances RF Verification While AWR Delivers an Improved Microwave Office How to Meet the Design Challenges of WiMAX Power Amplifiers Products Calendar

Microwave Engineering Europe - July/August 2008

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