Microwave Engineering Europe - July/August 2008 - (Page 18)

18 CAD/EDA Cadence enhances RF veriﬁcation while AWR delivers an improved Microwave Ofﬁce Edited by Jean-Pierre Joosting Cadence claims to have enhanced RF veriﬁcation Cadence Design Systems has introduced a new simulation technology to verify wireless integrated circuits implemented in advanced CMOS process nodes. Cadence has added the “turbo” technology it recently brought to the Virtuoso® Spectre® Circuit Simulator to its RF analysis. The result is performance improvements of two to ﬁve times for analysis and veriﬁcation of large RF circuits targeting advanced CMOS process nodes, and with no degradation in accuracy. This technology complements a complete manufacturability-aware solution from Cadence for design, implementation and veriﬁcation of RF integrated circuits (RFICs). Based on the Virtuoso custom design platform, this solution enables designers to deal with the challenge of integrating RF with analog/mixed-signal baseband, and the emerging need for RFIC-focused electromagnetic analysis. The complete solution includes the Cadence Virtuoso RF Designer, which brings a full-wave fast planar electromagnetic (EM) ﬁeld solver to the RF/wireless designer’s desktop. It offers designers advanced veriﬁcation capabilities for faster electromagnetic analysis of complex structures and geometries — all within a single design ﬂow, accelerating chip ﬁnishing and veriﬁcation. Virtuoso RF Designer integrates seamlessly into the Virtuoso front-end and leverages Cadence’s patented electromagnetic analysis technology to accelerate and accommodate large designs found in today’s RFICs and System-on-Chip (SoC). The Cadence RFIC solution provides an interactive link between system design and circuit design by integrating with Simulink from The MathWorks. Cadence Design Systems www.mwee.com/208800383 AWR improves Microwave Ofﬁce with 100+ enhancements With Version 2008 of the Microwave Ofﬁce® design environment, AWR® has made signiﬁcant changes to the user interface in order to increase its ﬂexibility for the user. The new version also includes APLAC® harmonic balance (HB) analysis software as an alternative non-linear HB engine within the Microwave Ofﬁce highfrequency design suite. The company reports that overall, hundreds of improvements have been made throughout the design environment. In Version 2008, the appearance of the overall interface can now be switched back and forth to appear much like Microsoft Ofﬁce 2000 or 2003. AWR explains that it made these changes to make it easier for users to customize the design environment to suit personal preferences, with the goal of streamlining various design tasks to save time and optimizing the screen space. The AWR-APLAC foundry-approved RF simulation capability was previously available only as an option in the AWR design environment, but now comes as a standard HB engine in Version 2008 for customers who license the HB capabilities of the Microwave Ofﬁce design environment. The APLAC engine is targeted at designers of complex, extremely nonlinear circuits and is based on a proprietary implementation of HB analysis that complements the frequencydomain simulation capabilities of Microwave Ofﬁce. It has been ﬁne-tuned based on more than 15 years of experience in RFIC design at Nokia and other device manufacturers, and AWR notes that it has been used in the design of more than 30 percent of all mobile phone RFICs. In addition to the user interface and APLAC enhancements, Microwave Ofﬁce software now incorporates ICED IC veriﬁcation software along with its support for Mentor Graphics Calibre®. Since the last major release, AWR has added advanced process design kits for TriQuint Semiconductor, WIN Semiconductors, and United Monolithic Semiconductors (UMS), and more are planned for the coming months. Version 2008 also features enhancements to AWR’s Visual System Simulator™ (VSS) software, which was integrated into the AWR design environment several years ago. This software suite aims to assist the end-to-end design and optimization of communications systems by enabling the impact of “real-world” signal impairments and other factors to be evaluated early in the design cycle when they can be addressed most effectively. VSS provides the tools necessary to optimize each of the components in a system architecture from the behavioral through component levels (in conjunction with Microwave Ofﬁce software or AWR’s Analog Ofﬁce® software), and then using actual device measurements to validate the ﬁnal design. VSS also includes an enhanced RF Budget Analysis™ tool, which enables the user to make traditional RF cascaded measurements along a communication link, that now uses a circuit solver and expands the range of supported topologies. Co-simulation with Microwave Ofﬁce, including the APLAC HB engine, is also now enabled. AWR www.mwee.com/208802767 Analog/RF mixed signal simulator Berkeley Design Automation has introduced a SPICE accurate analog/RF mixed-signal veriﬁcation based on co-simulation of its Analog FastSPICE™ circuit simulator with Verilog HDL simulators. Analog and RF design teams face increasingly difﬁcult mixed-signal veriﬁcation challenges. Complex blocks such as fractional-N PLLs, frequency synthesizers, and transmit and receive chains increasingly include complex digital logic. Nanometer CMOS ICs such as system-on-chips (SoCs), wireless transceivers, power ICs, and data converters have a rich mix of digital logic and high-performance analog/RF circuitry. Design teams need to verify their analog/RF circuitry with SPICE accuracy together with their digital logic using their standard Verilog simulator. The Berkeley Design Automation tools include Analog FastSPICE™ circuit simulation, Noise Analysis Option™ device noise analyzer, RF FastSPICE™ periodic analyzer, and PLL Noise Analyzer™ stochastic nonlinear engine. The company guarantees identical waveforms to the leading “golden” SPICE simulators down to noise ﬂoor (typically 0.1 percent or less) while delivering higher performance and higher capacity. It achieves this by using advanced algorithms and numerical analysis techniques to rapidly solve the full-circuit matrix and the original device equations without any shortcuts that could compromise accuracy. Berkeley Design Automation www.mwee.com/208802769 Microwave Engineering Europe ● July/August 2008 ● www.mwee.com http://www.mwee.com/208802767 http://www.mwee.com/208800383 http://www.mwee.com/208802769 http://www.mwee.com

Table of Contents Feed for the Digital Edition of Microwave Engineering Europe - July/August 2008

Microwave Engineering Europe - July/August 2008 Contents News Comment Cover Feature: Effective EM Simulations with Micro−λ Resolution in Macro-λ Objects — General Huygens Box Implementation RF CMOS: Programmable Transceiver IC Minimises OEM Inventory for Femtocells CAD/EDA: Software-Defined Radio Platforms CAD/EDA: Cadence Enhances RF Verification While AWR Delivers an Improved Microwave Office How to Meet the Design Challenges of WiMAX Power Amplifiers Products Calendar

Microwave Engineering Europe - July/August 2008

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