Microwave Engineering Europe - October 2007 - (Page 16)

16 CMOS RF plant. That move opened the way to multiple sourcing and expanded design libraries. The cornerstone of Peregrine’s SOS process is heteroepitaxial growth of singlecrystal silicon on sapphire (Al2O3). Lattice mismatch of the silicon with the sapphire substrate results in lattice defects, primarily so-called twin defects. Implanting the substrate with silicon to create an amorphous silicon layer near the silicon-sapphire interface is followed by solid-phase epitaxial (SPE) regrowth from the top silicon surface toward the interface. That enables the amorphous silicon layer near the interface to be regrown with minimal lattice defects. The silicon layer is then thinned by oxidation to consume remaining defects near the surface, eliminating twin defects and bandgap states and resulting in a pure single-crystal silicon layer for CMOS devise fabrication. It is formed on a single-crystal silicon ﬁlm that was previously grown on the sapphire substrate. By forming a recessed local-oxidation-ofsilicon isolation structure to separate active areas, well regions normally required for device isolation in bulk silicon substrates are not necessary. The combined footprint of the source, drain and channel is accordingly very small, minimizing junction capacitance. The early drawbacks of SOS technology included lattice mismatch, stress-induced delamination and poor interface quality. Die size was limited by substrate nanotopography, and lattice defect density added to the obstacles. These problems have been largely addressed and will continue to diminish. Today’s substrates are still limited to 150-mm diameters, and while surface roughness is less than 5 angstroms root mean square (compared with 1.5 Å rms for SOI substrates), these issues may still limit the level of integration possible with this technology for some time. Further, largediameter sapphire wafers add to the overall cost of the devices. On the positive side, SOS provides full dielectric isolation with no substrate capacitance, and no back gate is required. The higher thermal conductivity of sapphire eliminates self-heating effects inherent in the thermally insulated body of SOI devices. This improves backside cooling for ﬂip-chipmounted devices. Given that SOS technology can reduce complexity of SiGe-based processes by up to 50 percent, these advantages may override the drawbacks of SOS and provide a compelling enough advantage to control costs and entice designers. The PE42612 UltraCMOS SP4T switch is an antenna switch module that has been commercialized using SOS technology. The insulating sapphire substrate eliminates the parasitic drain capacitance, making devices like this one well-suited for use in triple- and quad-band GSM systems. Additionally, the integrated decoder/drivers made possible by the CMOS logic of the SOS technology eliminate the need for the ofﬂine decoders, blocking capacitors and diplexers normally required with other technologies. The device is manufactured using Peregrine’s single-poly, three-metal FA process and is ﬂipchip mounted. Early in 2006, Peregrine had already shipped more than a million devices for use in GPRS handsets. Increasingly complex and integrated switches, such as the SP7T HaRP SOS switch, are being designed and manufactured. About the author John Boyd (johnb@semiconductor.com) is product technology manager for process technology at Semiconductor Insights (Kanata, Ontario). He holds more than 60 U.S. patents. IMEC sets new record for 9 bit, 50 MSamples/s SAR ADC with a ﬁgure of merit of 65 fJ An ultra-low power (0.7 mW), high-speed (50 MSamples/s) analog to digital converter (ADC), presented by IMEC at this year’s ISSCC conference, achieves a ﬁgure of merit of 65 fJ per conversion step. This is 2.5 times better than the best ADC of this kind ever reported in research papers and an order of magnitude better than the best commercially available ADC IP blocks in 90 nm CMOS. IMEC’s successive approximation (SAR) ADC design is especially suited for nomadic applications in the IT realm. Its power scales linearly with the clock rate over a wide range which makes it ideal for softwaredeﬁned radio applications. It is implemented in pure digital CMOS technology, making it suitable for scaling to the 45 nm CMOS node and below. The design is available as ‘white box IP’ for transfer to the industry. The SAR ADC design is related to the what is claimed to be the world’s ﬁrst true softwaredeﬁned radio front-end IC also presented by IMEC at ISSCC 2007. This front-end chip is widely programmable for all present and future standards between 174 MHz and 6 GHz. Instead of the active charge redistribution in the capacitor arrays of a conventional SAR architecture, the low-power architecture of this SAR ADC uses a passive charge-sharing concept to sample the input signal and to perform the successive-approximation cycling. As a consequence, the SAR operation is no longer based on voltage comparisons. It operates completely in the charge domain, which yields the record performance of the new design. This way, the fundamental power limits of the original SAR architecture are overcome — by doing all the charge redistribution passively. The only active elements in the IMEC SAR ADC are the comparator and digital controller, so enabling ultra-low power consumption. Since the comparator doesn’t consume any power during inactive mode, the power consumption of the ADC scales linearly with the sampling frequency. The fully digital implementation of the ADC requires only MOS switches and metaloxide-metal capacitors, making the ADC scalable towards the 45 nm node and beyond. This latest SAR ADC from IMEC outperforms all state-of-the art commercial ADCs by a factor of 10. It is 3.7 times better than ADCs in the same process generation (90 nm) and it is by a factor 2.5 better than any other high-speed research ADC. www.imec.be Basic architecture Microwave Engineering Europe ● October 2007 ● www.mwee.com 014-016_MWEE.indd 16 20/09/07 13:02:12 http://www.imec.be http://www.mwee.com

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Microwave Engineering Europe - October 2007 Contents Comment News CMOS RF: Si-On-Sapphire Goes Mainstream Cover Feature: New Data Protection Concept for UHF RFID Tags CMOS RF: RF Design Team Touts CMOS Spin for 3G PAs Wireless HID – Are You Following the Standard to Another “Average” Product Development? Phase Optimisation of the RF Front-End Direct Synthesis of UWB-WiMedia Signal Generation 4G Chips to Target 700 MHz Applications Femtocells Mobilize to Fight Wi-Fi in the Home Products Product Feature: AXIEM Pioneers the Future of EM Technology Calendar

Microwave Engineering Europe - October 2007

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