Microwave Engineering Europe - November 2008 - (Page 18) 18 MMICs An 18 to 40 GHz double balanced mixer MMIC By Andy Dearn, Liam Devlin, Plextek Ltd, UK and Roni Livney, Sahar Merhav, Elisra Electronic Systems Ltd, Israel T his article describes a broadband, bidirectional mixer IC. The RF frequency range is 18 to 40 GHz, the LO 20 to 42 GHz and the IF 0.1 to 17 GHz. A double balanced passive topology is used to provide inherent isolation between all ports and good suppression of spurious outputs. On-chip RF and LO baluns are included to provide an interface between the single-ended ports of the MMIC and the differential signals required by the double balanced mixer. The IC was fabricated on the PP15-20, 0.15 mm gate length PHEMT process of WIN Semiconductor. With an LO drive of +10 dBm the mixer has a measured conversion loss of between 7 dB and 10 dB, depending on frequency. LO to IF rejection is > 30 dB. 1. Introduction The design requirement for the mixer was an RF range of 18 to 40 GHz, an IF range of 0.1 to 17 GHz and an LO input range of 20 to 42 GHz. A passive design was required, as the mixer needed to operate as both an upconverter and a downconverter. A doublebalanced design was selected to benefit from the inherent isolation it would offer between the RF, LO and IF ports and the improved suppression of spurious products (all even order products of the LO and/or the RF are inherently suppressed [1]). 2. Design and simulation The first consideration in the design process was the choice of mixer topology. A quadring resistive (or switching) mixer was chosen as it offers small size, good linearity [2] and high LO rejection. This topology has a balanced (differential) interface at RF, LO and IF ports, as depicted in Figure 1. The transistors (depletion mode PHEMTs) in the mixer are biased at 0 V Vds and therefore behave as switches [3]. The gate is DC biased at a point between 0 V (switching transistor in its low loss state) and pinch-off (switching transistor in its low loss state). An LO drive signal is then superimposed on the gate bias switching the transistors between their high and low loss states at the LO frequency. The selected MMIC process needed to have transistors that provided good switching performance to mm-wave frequencies and a short gate length PHEMT process satisfied this criteria. Initial simulations were undertaken assuming ideal baluns at all ports. This allowed the optimum device size and gate bias voltage to be selected for the mixer transistors (drain-source bias is 0 V as stated above). Choice of device size is a trade-off between low on-state loss (large gate width devices) and high off-state isolation (small gate width devices). The optimum gate bias voltage was determined to be -1.4 V. However, this was based on the nominal device models provided by the foundry and the optimum voltage would vary with process spread and with temperature. A direct gate bias scheme was therefore not appropriate and an on-chip active bias network was designed to set the gate bias voltage and provide a degree of compensation with process spread and temperature. The active bias network operates from a -5 V supply at a current of less than 2 mA. Figure 2: Multiple coupled line Marchand balun. At low frequencies the gate-source/ gate-drain capacitance of the PHEMTs in the mixer is small and the reactance is high. It is therefore straightforward to use a resistor to define the terminating load for the differential LO drive. As frequency increases the capacitive reactance at the gates reduces and the terminating resistance must be reduced if it is to remain the dominant load. At mm-wave frequencies this approach is no Figure 1: Quad-ring switching mixer. Figure 3: EM simulated, insertion loss and matches of RF balun, as a 2-port. Microwave Engineering Europe ● November 2008 ● www.mwee.com http://www.mwee.com
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