Microwave Engineering Europe - December 2007 - (Page 24) 24 WIRELESS SYSTEM ON A CHIP Analysis of electrical signal integrity in wireless SoCs Effective find and fix strategy: from RTL to successful layout By Francois Clement, Chief Technology Officer, Coupling Wave Solutions (Grenoble, France) he growing demand for cheap consumer wireless applications calls for unprecedented levels of integration. Huge digital IPs, such as microprocessors, digital signal processors, or encryption engines, are being assembled together with analog blocks – e.g. power supply control, data conversion and radio-frequency (RF) – LNAs, VCOs and mixers. The former, also known as the aggressor, generates lots of interfering noise, which gets disseminated through the entire system to finally degrade the operation of the most sensitive circuitry (the victim). The entire electrical signal integrity (ESI) mechanism is very complex. It affects digital operation through IR drop, cross-talk and delay, as well as analog and RF. For the latter, the impact is rather more complicated as a very small noise level will produce dramatic influences at any time – and not only in the neighborhood of specific signal transitions as occurs in the digital domain. Many scientific publications and commercial software solutions are addressing the impact of ESI on digital design. The remainder of this paper will therefore focus on analog/RF impacts. In summary, noise impacting analog and RF victims is produced by circuits manipulating large electrical signals at high frequencies. These aggressors are any combination of digital, analog or RF functions drawing significant amounts of current on the power supplies which, because of the various physical interconnect and package parasitics involved, result in considerable supply bounce. In addition, as illustrated in Figure 1, substrate noise injection happens across a wide range of various mechanisms – conductive through device bulks and substrate biasing contacts, capacitive from source-drain junctions or metal capacitances, in conjunction with wellsubstrate junctions. The noise disseminating across the whole system is further filtered when transferred through the RC substrate coupled to the RLC parasitics from both interconnect T Figure 1: ESI mechanisms involved in wireless systems. and package. The same parasitics also prevent a perfect grounding of sensitive circuitry, and a significant amount of noise eventually reaches victim devices through a combination of substrate, interconnect and package parasitics. Amongst all the challenges to address ESI impact on analog and RF victims, modeling noise generation and injection is particularly tricky. The issue is to collect the many power supply and substrate currents in both time Figure 2: Example of noise injected by a digital buffer: (a) input and output voltages, (b) supply currents and (c) bulk currents. Microwave Engineering Europe ● December 2007 ● www.mwee.com 024_025_026_027_MWEE.indd 24 21/11/07 14:59:42 http://www.mwee.com
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