Microwave Engineering Europe - December 2007 - (Page 25) WIRELESS SYSTEM ON A CHIP 25 all families of each cell in a standard library. On one side, existing noise models available in popular EDA flows – such as ECSM – tackle only power supply noise in the time domain. On the other side, recent publications considering analog/RF impact focus on substrate noise modeling, and are not compatible with the requirements of commercial software. In addition, interconnect is not the dominant and only crosstalk medium, unlike in purely digital applications. For analog and RF applications, as depicted in Figure 3, the simulation of noise propagation with various substrate types exhibits the comparable importance of capacitive and inductive coupling through interconnects and package above 1 GHz. Moreover, the impact of interfering noise on analog and RF victims is not limited to delay but ranges from poor biasing to full specification degradations – such as the noise figure of Figure 3: Simulation of noise propagated through substrate, LNAs, phase noise and spurs on VCOs, etc. – that require noise interconnect and package with (a) standard CMOS process modeling capabilities both in and (b) very high resistivity substrate. the time and frequency domains. To add even greater complexity, of course the respective impact of substrate, interconnect and package parasitics depends on the manufacturing being used, the design style – which in turn relates to the standard cells being used – and system specifications targeted. At the end of the day, only a dedicated software platform can help to address, effectively, ESI issues to detect system weaknesses early enough in the design flow and to determine the most appropriate solution. Figure 4: WaveIntegrity: CWS answer to ESI in wireless One can summarize the highsystems. level requirements for an EDA solution to ESI as follows: and frequency domains. Figure 2 illustrates a sample for the simplest possible cell: a CMOS buffer. The contribution here is for one specific set of input slew rate and output load conditions. In real life this has to be conducted over a wide range of operating settings, for • Ability to model any silicon and package manufacturing technology, • Pre-characterization of standard cell library contributions, • Unified modeling technology to process complex IPs as well as full systems, from early floorplanning to final layout verification, • Seamless integration into most popular design flows. The Coupling Wave Solutions (CWS) answer is a software platform called WaveIntegrity. As shown in Figure 4, all four tools comprising this set are based on common extraction and analysis engines. Dedicated to manufacturing data characterization, WaveMapper extracts parameters necessary to model, accurately, substrate and interconnect parasitics. WaveLibrarian automatically processes standard cell, core and I/O cell libraries to generate compact proprietary models, adding ESI to the set of existing cell descriptions. WaveModeler is a versatile IP block modeling tool that allows IP providers to communicate ESI parameters without giving out the heart of their intellectual property. WaveAnalyst is an investigation solution which helps designers to analyze and enhance the robustness of complex systems and IP blocks, from RTL to final layout sign-off. For maximum performance and capacity, WaveMapper and WaveLibrarian are used to collect the most important characteristics driving the injection and propagation of noise. WaveMapper is run once for every process to extract the substrate and interconnect characteristics necessary for the 2.5D extraction engines. Besides the significant extraction speed-up benefit provided by this pre-processing, the technology mapper brings an increased protection to commercially very sensitive foundry IP by compacting doping profiles into information that prevents reverse engineering. WaveLibrarian automatically reads behavioral and spice descriptions, together with abstract and full layouts of standard cells, to compute a proprietary ESI macro-model. This includes noise contribution in the form of power supply and substrate sources, as well as a passive RC model providing a link between all sources and the cell periphery – see Figure 5. During the characterization process, many noise figures are collected. To speed up system level analysis and at the same time limit the size of the final data base, a reduced set of harmonic equivalents – such as the one shown in Figure 6 – is eventually stored. This simplification mechanism allows efficient reconstruction in time and frequency domains during complex IP or full system analysis while preserving the precision level.* For each cell, the exhaustive set of injection conditions is explored by varying input vectors and input slopes as well as output loads. At the end of all simulations, a proprietary algorithm allows the determination of the worst, and Figure 5: The sample noise model extracted by WaveLibrarian for a simple standard cell.* Microwave Engineering ● December 2007 ● www.mwee.com 024_025_026_027_MWEE.indd 25 21/11/07 14:59:59 http://www.mwee.com
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