Microwave Engineering Europe - December 2007 - (Page 26) 26 WIRELESS SYSTEM ON A CHIP Figure 6: The sample supply noise extracted by WaveLibrarian, observed in the CWS post-processing GUI. least injection figures, as well as a statistical typical behavior. Significant challenge A significant challenge in modeling noise generation, from early in the design flow to final layout, is the varying level of details available. The most detailed data is only obtained at the final stage, when many kinds of information are accessible – physical layout with final placement and routing, signal delays and gate loads – through various standard formats (GDSII, DEF, LEF, SPEF, DSPF …). Adversely, before entering the physical system assembly, the available information can be as limited as approximated number of gates and estimated area, as well as power supply and clock domain assignments. To overcome the lack of detailed information at this stage, specific algorithms are necessary to provide an estimation of noise in these conditions. Of course, as depicted in Figure 7, the level of accuracy will vary, reaching the best possible model only when the final layout is known. For instance, it is not possible to assess the exact operation conditions (delay, gate loads) until the final layout. Even before, early in the flow, the detailed netlist is not known, adding more uncertainty Figure 7: The noise estimation challenge: the level of detail evolution impacts the accuracy. Figure 8: With WaveIntegrity graphic post-processor, interconnect and substrate geometry (left) as well as propagation netlist (right) can be explored. to the noise injected by a particular IP block. Therefore, a specific methodology is required to overcome the limited accuracy available early in the flow. The CWS answer to system noise model utilizes the pre-characterized standard cell data to propose, independent of the level of detail provided, three noise representations: worst, typical and best noise figure. Thanks to the application of a common set of technologies throughout the flow, the worst and best case estimation will converge when the physical description gets closer to the final layout. CWS noise modeling algorithms take advantage of the statistical information that might be extracted from existing designs (typical cell usage, statistical delay and load distribution, etc.). Later on, as detail becomes known, estimations are replaced with actual data and the whole system description is processed using the same technologies. This method ensures the necessary convergence of worst and best cases toward the typical noise obtained only after final layout.* This way, noise can be estimated far before the physical implementation to help in making critical decisions. In fact, if worst case noise analysis does not raise any ESI issues, it is safe to carry on, and very likely that first silicon will be free of cross-talk. Adversely, if best case estimation flags potential interference concerns, proceeding to physical implementation is extremely risky and severe corrections are required which might motivate high-level choices such as package, architecture, etc. The propagation model is automatically computed from a layout description. The resulting netlist – combining self and mutual RLC parasitics of substrate, interconnect and package – can be explored using a dedicated visual aid as depicted in Figure 8. This transfer function is pulled together with the system level noise to save a comprehensive model of interfering noise. Therefore, a proprietary analysis engine simulates the amount of noise reaching user-defined monitoring nodes in the system. The output can be visualized in the time and frequency domains as demonstrated in Figure 9. Detection by measurement In the past, before any software solution was available, all failures related to interference in mixed digital/analog/RF systems were detected by measurement; moreover finding and fixing the issues was extremely uncertain. Yet, the availability of early noise estimation can not always prevent iterations from final layout back to functional re-design. Figure 9: Example of interfering noise visualized in WaveIntegrity explorer in time (a) and frequency (b) domains. Microwave Engineering Europe ● December 2007 ● www.mwee.com 024_025_026_027_MWEE.indd 26 21/11/07 15:00:16 http://www.mwee.com
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