Microwave Engineering Europe - December 2007 - (Page 27) WIRELESS SYSTEM ON A CHIP 27 Because functional simulators lack the actual descriptions of noise reaching victim blocks, re-spins occurs over lengthy and tedious re-design loops encompassing functional and physical implementation – see Figure 10 (a). The solution provided by CWS is to automate the feedback of noise figures computed during ESI analysis within popular functional simulators – such as Eldo, EldoRF, Spectre or the like. As a result, it is now possible to assess the victim’s immunity to actual noise. Existing circuit design techniques can therefore be applied more effectively during function implementation to reach the best possible noise margin. As pictured in Figure 10 (b), the physical implementation loop thus has a dramatically greater chance of concluding ESI analysis successfully. In addition, WaveIntegrity incorporates calibration mechanisms which bring improved high-level noise estimation after silicon failures. This feature is yet another key factor to ease the investigation and to increase the effectiveness of solutions to the most difficult ESI problems. As an application example of the automated back-annotation, the simulation of parasitic noise spurs produced on a LC-tank VCO is presented in Figure 11. Detecting ESI issues is critical but not sufficient. Whenever interfering noise monitored with WaveAnalyst – and/or backannotated within functional simulation – demonstrates unacceptable electrical behavior, one faces a tedious investigational challenge. One aspect is covered using the backannotation to improve the victim immunity with respect to the back-annotated interfering noise. Another aspect is to decrease noise generation and propagation. Within Figure 10: Lengthy and tedious re-design loops (a) can be limited to separated functional and ESI verfications when noise analysis results are fed back into functional simulations (b). WaveAnalyst this investigation process is helped thanks to a couple of dedicated postprocessing engines. The graphical explorer depicted in Figure 8 allows designers to visualize the propagation geometry and to explore the parasitic netlist. This helps to solve the most obvious design errors, such as incorrect connection of isolation structures (open circuits, shorts with noise interconnects) as well as power supply grid problems. In addition, for each monitoring node, a list of major aggressors, sorted by order of decreasing influence, can be produced. With this inventory, it is possible to identify a limited set of noise injectors whose influence must be decreased. This can be achieved by applying various known design techniques – selection of low noise alternates, use of separate power supplies, relaxation of clocking. Last but not least, when the former solutions have been applied but the noise reduction is not sufficient, the transfer function from one single noise source to a specific monitoring node is analyzed to determine the most effective corrective action: addition/modification of guard rings, use of manufacturing features (triple wells). When all techniques above have failed, then the system might not be feasible without a dramatic change such as selecting a more expensive package, or entering system and architecture re-design. ESI issues, occurring when assembling RF and/or analog circuits on the same die or within the same package as inherently noisy blocks (such as large digital processing functions), are extremely complex. Such issues traverse many design phases – are not restricted to the final physical implementation – and often involve designers with very different levels of expertise (analog, RF and digital at system and block levels). Overall, the many post-analysis tools within WaveIntegrity offer a powerful guide to detect, fix and verify ESI issues through effective what-if analysis before entering the costly production stage. The level of automation involved in the tool allows any designer to get quickly up to speed, even with very limited expertise. Moreover, the automatic back-annotation of interfering noise within functional simulation provides an easy (and welcome!) communication channel between digital, analog and RF designers. Figure 11: Example of automated back-annotation of WaveIntegrity simulated noise during the functional verification of an LC-tank VCO. * Patents are pending on this technology. Microwave Engineering ● December 2007 ● www.mwee.com 024_025_026_027_MWEE.indd 27 21/11/07 15:00:36 http://www.mwee.com
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