Microwave Engineering Europe - December 2008 - (Page 28) 28 PCB DESIGN close proximity and lots and lots of ground vias. You will also be able to know the tolerances for success and tune the RF circuit shapes so that the manufacturing tolerances has as little impact as possible on the overall RF performance thus increasing yield and squeezing costs. To achieve a concurrent design flow, you need a tool integration that is so robust and so fast that it takes practically no time to copy a design from the RF design environment to the board environment, and back again, to validate changes. The previous IFF based solutions could never reach that level of integration as the tool sets are too different. New tool integrations open up for a flow where an RF circuit can be sent on multiple round trips between the RF design environment and PCB environment without loss of design intent. Now designers can truly collaborate. It means for example that the RF circuit that might physically be too long to fit on the board, can be “bent in shape” to fit while in the PCB tool and the effects be simulated immediately in the RF tool followed by posting back parametric updates to adjust the circuit. In our story, this means that as several PCB designers are working simultaneously on the same design database to implement the analog and digital portions, the RF designer can also work on the same design database to fit in the RF modules onto the PCB and validate their operation the context of the complete board. The RF engineer will use parametric RF shapes in combination with custom designed metal shapes to realize the RF circuit. Custom shapes are characterized by extracting Sparameter models. The parametric shapes have parametric circuit-level models thus providing very fast first order analysis of the circuit. The simulated circuit can be driven by complex signal sources such as modulated cell phone or Wi-Fi signals and the result be monitored as if a real RF/microwave instrument such as a network or spectrum analyzer was connected to a real circuit. When the circuit operation is satisfactory, the design is pushed over to the board environments schematic and layout to make the RF circuit a real intelligent part of the design, not just a black box. It’s almost a rule that the RF module will not directly fit on the PCB. Space is constrained and frequently the PCB designer has to make trade offs to be able to fit in all the parts. For RF, this often means modifying the circuit by splitting it into several separate smaller blocks, bend, or fold it. All these operations will impact the circuit operation and the RF Designer will have to assist with suggestions about how to modify the circuit and to verify by simulation that the changes are okay. In this process, the design is sent back and forth between the RF tool and the PCB tool multiple times and changes are applied in both environments wherever it makes the most sense in each case but regardless, it is always brought back to the RF environment for verification. As the PCB gets closer to completion, the PCB designer adds ground planes and power planes. The RF engineer will want to have a say in how close to the RF shapes the planes may go and sometimes, decide on nonuniform spacing, such as a tapered ground plane clearance. Left to do in the PCB domain is to add ground stake vias. We do this in two separate cases and for different reasons. First, as RF current is flowing in the ground planes, we risk something called parallel plate excitation which can cause RF energy to radiate. The PCB designer peppers the ground planes with ground vias tightly spaced to short out this effect. The spacing and hole diameter is important and the RF engineer will want to simulate this when we are done. RF transmission lines will also radiate RF energy. Clearly we don’t want RF energy radiating from unintended sources, but equally important is to minimize losses in the transmission lines due to the radiation. The PCB designer stitches tightly spaced rows of ground vias along the printed transmission lines to minimize the losses. The circuit operation is also impacted by the ground plane structures and the ground vias and the RF engineer will now want to verify that we are still operating within specifications. This requires a detailed electromagnetic analysis so we need to transfer the PCB structure with an accurate description of the ground planes and the ground vias as well as define simulation ports for all connection nodes. With the board layer stack up transferred at the same time, the circuit is instantly ready for electromagnetic extraction in the RF tool. The generated multi-port Sparameter model can now be used to verify the real implementation of the circuit together with the packaged parts on the board. In summary, a parallel design flow with tightly coupled simulation and design provides the foundation to reach design closure much faster and with fewer iterations. Users of this flow have reported the potential for cutting the design times in half and with increased level of quality. This article has been reprinted courtesy of RF Designline www.mwee.com/212200828 Can the analog foundry model work? By Svenn-Tore Larsen, CEO, Nordic Semiconductor In theory, digital chips can be moved around from one manufacturing facility to another. For example, a chipset can be built at IBM, TSMC or even SMIC. Because you can clone a ‘’mask set’’ from the chip, the industry made that practice illegal via the Semiconductor Protection Act (SPA) in 1984. So, even though someone can steal your design and make it, selling it in any reasonable quantity on the open market is a dead end. In the case of analog parts, the above considerations do not apply. Analog and mixedsignal parts are specific to individual production lines. Generally, they cannot be moved from one line to another without recalibrating the process from scratch. The reason is simple. Analog devices do not come off the line in a ‘’binary’’ state. If you think of an analog part (discrete), they come off the line in a range of values. What a discrete maker does is bin them and sort them for different markets. Think of an analog IC as a collection of hundreds to millions of little analog devices. Each have their own bell curve, and you have to get the entire collection ‘’within spec’’ for the IC to work. If you were to even restart the line in the future, the line has to be recalibrated. That’s not hard to do if you have the same crew and the previous process data. On the other hand, if you don’t own the line and use a foundry, you have the following hurdles: 1) There is no assurance that the tool set is identical; 2) There is no assurance the line workers will be the same; 3) There is no assurance of a full set of data. What you find is that detailed technical knowledge required to make a qualified and good part is in the hands of your foundry partner. In other words, you end up in a monopolistic relationship with the foundry. So, there is virtually no difference than if you actually owned the facility in terms of costs and risks. Add this up and the advantages of a foundry disappear pretty fast. That is why the analog/mixed-signal foundry sector will always be a small market. The exception could be low-end, non-critical parts; in that case, the device maker doesn’t mind not being in control of manufacturing. We will retire before we see the day TI, ADI and others hand over their top-of-the-line analog and mixedsignal parts to a foundry to make. This article has been reprinted courtesy of EE Times www.mwee.com/212000524 Microwave Engineering Europe ● December 2008 ● www.mwee.com http://www.mwee.com/212200828 http://www.mwee.com/212000524 http://www.mwee.com
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