Microwave Engineering Europe - December 2008 - (Page 32) 32 PRODUCTS Base station receivers targeted with 16-bit ADC and dual-channel DVGA Two high-speed signal path products, a 16-bit, 130 MSPS ADC and a digital-controlled variable gain amplifier (DVGA), have been introduced as part National Semiconductor’s PowerWise® family. They claim the industry’s best linearity performance and lowest power for multi-carrier GSM and multi-carrier, multi-standard wireless base station receivers. The 16-bit ADC16V130 exhibits spurious-free dynamic range (SFDR) performance with 90.6 decibels full scale (dBFS) for a 160 MHz input frequency, and 87 dBFS guaranteed. It provides high-order harmonic distortion performance at any input frequency, and consumes 755 mW. The LMH6517 dual DVGA provides a 1.2 GHz bandwidth, along with a third-order output intercept point of +45 dBm and a noise figure of 6 dB. According to the company at 400 mW per channel, the LMH6517 consumes 33 percent less power than the nearest competitive DVGA. The ADC16V130 is a high-speed ADC capable of converting analog input signals into 16-bit digital words at conversion rates up to 130 MSPS. The ADC uses a differential pipelined architecture with digital error correction and an on-chip sample-and-hold circuit to minimize power consumption. It also provides full-power bandwidth of 1.4 GHz and a SNR of 78.5 dBFS at 10 MHz input frequency. The device includes powerdown and fast recovery, and features industry-standard lowvoltage differential signaling (LVDS) outputs for interfacing to field-programmable gate arrays (FPGAs) and application-specific integrated circuits (ASICs). The ADC16V130 operates over the -40 to 85 degrees Celsius range and is supplied in a 9 mm by 9 mm, 64-pin LLP package. The LMH6517 is a dualchannel DVGA designed for use in narrowband and broadband IF sampling applications. It offers a gain range of -9.5 dB to 22 dB in 0.5 dB steps to optimally scale the received signal and maximize the available signal path dynamic range for the ADC. The amplifier’s differential input supports differential-todifferential or single-ended-todifferential operation. The LMH6517 operates over -40 to 85 degrees Celsius and is supplied in a 5 mm by 5 mm, 32-pin LLP package. A reference board that includes the ADC16V130 and LMK04031B clock jitter cleaner interfaces directly with National’s new WaveVision 5 software and data capture board to simplify the evaluation process. www.mwee.com/212200822 Any-rate, any-output clock generator claims industry first dramatically simplifies timing architectures by replacing four discrete phase-locked loops Silicon Laboratories has introduced a family of clock generators and buffers that provide a high degree of frequency flexibility. Based on the company’s breakthrough MultiSynth™ technology, the Si5338 is capable of synthesizing any frequency from 0.16 to 350 MHz and select frequencies to 700 MHz on each of the device’s four differential outputs, dramatically simplifying timing architectures by replacing four discrete phase-locked loop (PLL) devices with a single IC. At one picosecond rms random jitter typical, the Si5338 is able to simultaneously generate low jitter clocks for a wide variety of ICs, including processors, FPGAs, ASICs, memory and physical layer transceivers. The device generates four differential or eight singleended outputs per device, eliminating the need for external clock distribution buffers. In addition to frequency, each output clock is independently configurable in terms of supply voltage (1.5 V, 1.8 V, 2.5 V, 3.3 V) and signal format (LVPECL, LVDS, CMOS, HCSL, SSTL, HSTL), eliminating the need for external level translators and thereby reducing BOM cost and complexity. Historically, complex timing architectures have required multiple clock generators and/or standalone crystal oscillators (XOs) to provide the range of frequencies needed by the end application, often at the expense of cost, design complexity and power. The any-rate, any-output capability provided by the Si5338 dramatically simplifies timing architectures by replacing fixed frequency clock generators, discrete level translators and crystal oscillators with a single device, minimizing cost and real estate and reducing power by 50 percent compared to traditional solutions. To simplify board-level test, the clock generator includes a frequency margining feature that enables the frequency of each output clock to be varied dynamically over the 0.16 to 350 MHz range, eliminating discrete XOs and making it easier for hardware designers to guarantee consistent, reliable system operation over temperature and voltage. For applications that do not require the programmability provided by the Si5338, the company is also introducing a broad portfolio of Si5334 pincontrolled clock generators. More than 70 Si5334 devices are available for popular Ethernet, Fibre Channel, PCI Express, T1/E1, broadcast video (HDTV) and SONET/ SDH OC-3/12/48 applications. In addition, the company is introducing the Si5330 family of low-jitter, low-skew clock buffers that support the widest range of output clock formats in the industry. The flexible clock buffer produces 4 or 8 buffered copies of the input clock and is available in both differential and single-ended versions. www.mwee.com/212000555 Microwave Engineering Europe ● December 2008 ● www.mwee.com http://www.mwee.com/212200822 http://www.mwee.com/212000555 http://www.mwee.com
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