Microwave Engineering Europe - March 2009 - (Page 12) 12 FOCUS ON RADIO image response to reduce any blocking signal falling on these frequencies. Lumped element The anti-alias filter was a lumped element filter. The initial prototype was a 7th order elliptic design. A requirement for higher rejection was then needed so 2 extra sections were added and Ansoft Designer circuit simulator’s optimiser used to generate a filter with the necessary pass and stop band requirements. The filters showed amplitude and group delay variation better than ±0.2 dB and ±3.5 ns. The measured pass band responses of a number of filters with adjacent amplifier stages are shown in figure 4. Rejection is achieved around ±40 MHz from band centre to reject signals that could alias on top of the wanted signal in the ADC. The zeros were clustered closer to pass band leading to better rejection in this band and less rejection further out, but when combined with the 650 MHz filter response this achieved the required rejection. Provision is made to switch between two different anti-alias filters. This means better pass band flatness can be achieved for the same rejection when a wide range of sample rates is required. The filter rejection gets worse again above 370 MHz due to the effect of parasitic inductor capacitance, and lead and via inductance. There is need for good rejection around 700 MHz due to LO leakage from the 3rd mixer so a small higher frequency low-pass filter is used after the mixer to mitigate this issue. Microstrip A low pass microstrip filter is used for rejection of out of band spurious frequencies above 4 GHz. It was designed by approximating a 9th order low pass LC filter prototype with open ended stubs connected with high impedance line. This was later extended to 11th order to improve high frequency rejection. Starting with the equation for the impedance looking into a transmission line [2] of length l and load ZL: Figure 5: Simulated and measured microstrip low-pass filter responses. Similarly a thin line l << λ/ 4 and ZL, << Z0 can be seen as an inductance of approximately: These approximations were used to get initial values for the microstrip elements from an LC prototype. Microstrip Ts and steps were then added to the circuit model. One stub was made longer so it was λ/4 at ≈6 GHz, while thinned to bring its low frequency capacitance back down. This way it presented a short at the frequency, placing a zero nearer to the stop band and therefore creating a sharper transition. The circuit simulator optimiser was then used to tune the response. The design was then verified with the electromagnetic (EM) simulator. The implementation can be seen at the bottom middle of figure 1 and the response in figure 5. Coupled line microstrip filters [2, 3, 4] were used at 4 GHz and 8 to 13 GHz for spurious rejection in local oscillator doublers. A combination of filter design tools, circuit and EM simulators were used. Two implementations of such filters can be seen in figure 1. Synthesiser Phase noise performance was an important issue but VCOs were used over YIG oscillators to avoid the cost, size, power, and tuning speed issues despite the superior phase noise offered by a YIG. High locking speed is required to allow use with frequency hopping systems. The required performance was met with good synthesiser design. The first LO required www.mwee.com Approximating for a short open ended stub l << λ/ 4 and Z0, << ZL , ignoring fringing, and equating with reactance of a capacitor to find the equivalent capacitance C looking into that stub: where v is the wave velocity in the microstrip. Microwave Engineering Europe ● March 2009 ● two switched VCOs to cover the full tuning range with 150 MHz overlap. The actual LO frequency was created by doubling the output from the synthesiser board. The use of a doubler instead of fundamental frequency VCOs allowed improved noise performance to be achieved while covering the whole tuning range with only 2 switched oscillators. To keep synthesiser noise to a minimum the PLL is operated with a divide ratio of N=1. This is achieved by mixing the VCO with frequencies taken from a low noise multiplier chain and using a DDS device to drive the PLL reference. Using large frequency steps from the DDS allows the use of a large loop bandwidth, which reduces the phase noise towards that of the reference over a larger band, while achieving a low spurious output. Pre-steering using a DAC is used to guarantee locking to the correct frequency and to speed up frequency lock time. A calibration procedure is used to build the table of DAC settings. Phase noise is –100 dBc at 1 kHz and –118 dBc at 100 kHz. A plot is shown in figure 6. It changes channel within 400 µs. The other synthesisers (LO2, LO3, ADC clock) use similar topologies but with simplified mixing and steering due to narrower tuning range. Their reduced tuning range requirement allows oscillators with much better phase noise to be used. The LOs have progressively smaller frequency step size but the final 1 Hz resolution is achieved using a numerically controlled oscillator (NCO) implemented in the digital section in an FPGA. http://www.mwee.com
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