Microwave Engineering Europe - March 2009 - (Page 13) FOCUS ON RADIO 13 Digital signal processing The final IF is sampled with a 16 bit ADC giving a high dynamic range in the digital domain. This is required for two reasons. It allows ±20 dB of power variation from the unit under test to be handled without the need for analogue ranging, while leaving enough back-off for modulation schemes such as OFDM with 64-QAM sub-channels. Secondly to allow good adjacent channel and blocking performance with narrow (e.g., 2G) signals without the need for switching in filters into the analogue path. In this case the analogue radio is kept simple and general purpose by performing the channel filtering in the digital domain. There are two Altera Stratix II FPGAs in the transceiver that perform the final stage of down-conversion to complex baseband. The NCO used for this tunes out the residual frequency offset caused by the synthesiser steps size and is used to achieve the 1 Hz frequency resolution. A gigabyte of on-board flash is available to hold calibration constants and filter coefficients. The FPGA can then take these constants and apply the gain correction and perform filtering. A high speed serial interface using Altera’s SerialLite protocol is available to transfer the data at sample rate to additional processing hardware. This processing can then be configured for channel filtering, decimation, and the demodulation as required. Calibration There are two main issues to be addressed with calibration. Wide band absolute power accuracy over the tuned 0.4 to 4 GHz range, and gain and phase flatness over the IF bandwidth. The wide band case is computationally straight forward as it simply requires a table of gain offsets with a frequency granularity that has been determined to be good enough for the accuracy required. Care must be taken to understand the inherent uncertainties in the reference used for the calibration and the added uncertainties due to impedance mismatch. It is complicated by requiring another dimension to the table: attenuator setting. As the attenuator setting changes it will not change in exactly 10 dB steps for example. Its attenuation and return loss may vary over frequency which will in turn affect the amplitude flatness over the band due to the change in mismatch between components in the system. Although best efforts were taken to keep the analogue filter gain and group delay as flat as possible across the band of interest it may be necessary to improve on this. Provision Figure 6: Measured phase noise of LO1. was made to electronically switch the signal path around the filters to auxiliary connectors. This allows an external network analyzer or the spare DAC/ADC to measure the response of the filters. For the accuracies required it is possible to measure the phase like this but the change in signal path and mismatch begins to add significant errors to the gain measurement. This means high accuracy gain flatness must be measured with the filters switched in circuit. The synthesisers are capable of tuning in smaller steps with reduced noise and spurious performance for this purpose. Another issue with the IF filter response measurement is the effect of the filters’ terminating impedance changing when a stepped attenuator is altered. This causes small but significant changes to the pass band response of the filter. Where this is a problem it is mitigated by adding extra fixed attenuation and amplification. Unfortunately many wideband gain blocks have a significant |S21| • |S12| product which means a change in the reflection coefficient on the output has a significant effect at the input. If this problem were not fixed in the analogue electronics there would need to be an attenuator dimension added to the filter tap table. Once the filter response has been measured a suitable set of taps for a digital equaliser can be calculated. These responses could be combined and one equaliser used but this would require many different filter coefficient sets to be calculated because of the various frequency offsets possible between the filters. Alternatively there can be a separate digital equaliser for each analogue counterpart. Conclusion A high performance general purpose radio platform has been developed that is adaptable for use with a wide range of communication standards. A synthesiser design based around off the shelf VCOs switches channel within 400 µs and achieves phase noise of –100 dBc at 1 kHz and –118 dBc at 100 kHz. The analogue design has been optimised to provide low amplitude and group delay variation. Higher accuracy is obtained with calibration and digital equalisation. An uncalibrated analogue section has been verified with 2G, 3G, and preliminary LTE test equipment. The on-board FPGA hardware and high speed digital link give the highest flexibility by allowing the final conversion, filtering, and demodulation to be defined in software. References [1] L. Devlin. “RF filter design using coupled co-axial resonators”. Presented at the RF and Microwave Society (ARMMS) conference, (April 2004). [2] T. H. Lee. Planar Microwave Engineering. Cambridge University Press, Cambridge, (2004). [3] R. Levy. Classic Works in RF Engineering Volume 2 - Microwave and RF Filters. Artech House, Norword, Massachusetts, (2007). [4] R. W. Rhea. HF Filter Design and Computer Simulation. Noble Publishing, Tucker, Georgia, (1994). Microwave Engineering Europe ● March 2009 ● www.mwee.com http://www.mwee.com
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