Microwave Engineering Europe - March 2009 - (Page 25) MODELLING 25 DataSource Transmitter Figure 2: A system composed of a transmitter and a receiver. Compare Channel Sink The three following modules are more specific: • ChannelInvert: this function performs the classical channel inversion by canceling certain effects of the air channel based upon measures of the frequency profile of the channel. • Demap: this function tries to find in the constellation pattern to which bit corresponds the received symbol. • Decoder: the decoder takes the final decision concerning the value of the received bits using a Viterbi algorithm. Application modeling Testbench modeling: THALES’s application model structure is derived from the functional design study detailed before. The testbench consists of two radio channel simulators (channel 1 and channel 2), a data source, a data sink and a comparator checking received data against the originally sent data. Shown in the figure 5 (available on line at www.mwee. com/214600264). Similarly, the receiver subsystem shows two receiver heads for simulating spatial diversity reception. A choice is made to model all communications between modules as FIFOs, since this is typically the case, even at the hardware level. Communications between a modem system-on-chip (SoC) or board and the higher-level data sender/receiver is frequently done through a physical FIFO, in order to disconnect the real-time data transport rhythms from the upper data exploitation level. This is also true for the data sent from the emission output of the modem to the radio channel, as well as data received to the reception input of the modem from the radio channel. Receiver A common practice is to use a FIFO on these links to limit the effect of a strictly clocked (on a bit basis) hardware transceiver part on the modem chip. Two solutions are envisaged: one uses FIFOs and the other does not. In the real world, the latter requires a more complex transceiver part. Modem functional architecture: The models for transmitter and receiver were deduced from the internal functional organization of the solution. Figure 6 and 7 (available on line at www.mwee. com/214600264) detail the transmitter and receiver subsystems. Execution platform modeling In order to study the performance of the system, the identified physical architecture is described in the following figure. This executive structure is composed of two processing units: one software unit for functions having relatively high activation periods and a hardware unit to support the high-frequency activated functions. The chosen hardware platform for the test case is dedicated to simulation and validation purposes in the analysis and design phases of the high data-rate modem. It consists of a general purpose processor (GPP) and a digital signal processor (DSP), which is to be selected later – see figure 8. Each processing unit is parameterized by its attributes. A link simulating the bus between the microprocessor and the ASIC is used for the hardware interconnection. The partitioning of the different 802.16 modem application components (allocation of the functions to the DSP) is done according to the performance constraints (data rate, required number of processors, power consumption). The created model has multiple possibilities for data paths, which can be individually selected to experiment with various possible hardware choices. Three main hardware options are compared. The circulation of data frames inside the GPP or DSP is not modeled in hardware. In a completed device, it is done by passing a memory pointer from one software module to another on the same processor. This operation requires no significant time, typically less than ten processor cycles. The changes are on the modem’s interfaces to the outside world, at the data source/destination on one side, and at the radio hardware interface on the other side. Data circulating to and from the modem and between processors uses models of hardware links. Timing information for such links is introduced in the link definition. The hardware FIFOs are defined to have a size of 3 frames, and the bus has no FIFO (size of 1) which indicates that every access to the bus must ensure it is free. If not, it must wait for the bus to become free. None of the interfaces has concurrency (i.e. only one transfer running on every link at a given time). It is necessary to get the timing effects of bus contention, in a model where a non-trivial part of data circulation occurs through a shared bus. Mapping & architecture exploration Several models of the high data-rate 802.16 modem are modeled at different abstraction levels, according to the MARTES methodology. An example of a mapping of the modem function onto the platform and the distribution of functions between the DSP and GPP is shown in figure 9 (available on line at www. mwee.com/214600264). For high level and radio interfaces on the bus all data is exchanged via the multiple access bus on the modem. No specialized link is used in the design. Data comes from the testbench (external world) into the DSP via a bus port. It is passed back and forth between the DSP and GPP via the same internal bus with possible priorities, and then goes to the physical transmitter via the same bus. Coder Decoder Puncture Depuncture Interleave Deinterleave Reshape Demap Modulator H-1 IFFT FFT PrefixAppend PrefixRemove Top — Figure 3: The transmitter module structure. Bottom — Figure 4: The receiver module structure — partially symmetric to the transmitter module. Microwave Engineering Europe ● March 2009 ● www.mwee.com http://www.mwee.com/214600264 http://www.mwee.com/214600264 http://www.mwee.com/214600264 http://www.mwee.com/214600264 http://www.mwee.com/214600264 http://www.mwee.com/214600264 http://www.mwee.com
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