EE Times Under the Hood - June 23, 2008 - (Page U58)

UTH0623SEMI_pg58_68.qxd 6/10/08 4:15 PM Page 58 under the hood: w w w. e e t i m e s . c o m SEMI CONDUC TORS • w w w. t e c h o n l i n e . c o m 45 nm: What Intel didn’t tell you BY DON SCANSEN sition. It is now well-known that Intel uses a gate-last, or replacement-gate, process flow at 45 nm. But even that provides opportunity for a debate on semantics: whether it’s “gate” or “last.” The replacement gate flow allows Intel to reuse process steps and tools from the age-old polysilicon gate technology. The process of patterning polysilicon and forming traditional silicon incorporates high-k-first, metal-gateThe gate dielectric is hafnium oxide last integration. Gate-last integration is oxide and nitride sidewall spacers lever(1-nanometer equivalent oxide thickages tried-and-true self-aligned processness). The process uses dual band-edge one point that needs clarification. es for source and drain formation and The terms “first” and “last” refer to work-function metal gates (TiN for the order of the high-k and metal gate their lightly doped extension regions. PMOS; TiAlN for NMOS). formation in light of polysilicon depo- Once those steps are completed, the This 45-nm HKMG technology polysilicon is removed, and work-function metals are deposited in their stead. Intel Penryn PMOS transistor structure But something interesting is going on even before the first poly deposition. Contrary to the suggestion in its paper at the International Electron Devices Meeting (IEDM) last December, Intel deposits the first work-function metal Second metal gate layer deposited into gate trench (replacement gate) prior to the sacrificial-gate polysilicon. For the p-channel transistor, TiN is First layer of work function metal gate deposited prior to polysilicon Sacrificial polysilicon dimension (45 nm) HfO2 high-k dielectric I ntel Corp. has built its 45-nanometer process technology around a combination of techniques. The process incorporates a high-k hafnium-based dielectric material, while using titanium nitride for the PFET replacement gate and a TiN barrier alloyed with a work-function tuning metal for the NFET replacement gate. LG measurement 0.346-square-micron SRAM cell 0.36µm Bird’s beak created by gate-last process 1.03µm Tungsten metal 1 Gate metal • Using the location of electrically active MG materials, we measure LG = 37 nm • After calibrating Intel’s published images, SI believes Intel uses a similar point to determine LG SRAM layout at tungsten metal 1 The strictly rectangular, parallel metal gates (medium gray) are visible below the tungsten lines, which appear brighter in this image 58 Electronic Engineering Times, TechOnline | June 23, 2008 http://www.eetimes.com http://www.techonline.com

Table of Contents Feed for the Digital Edition of Under the Hood - June 23, 2008

Under the Hood - June 23, 2008 Extreme Design: SuitSat Pushes Desigers' Limits Evolution of the Smart Phone Mature Devices get Rolly Rocking GPS: Garmin Nuvi 750 vs. HP iPaq 310 Inside the Sony OLED TV Multizone Dgital Audio Flip Ultra Camcorder - An Ode to Clean Design Robot Guitar Tunes Itself E-book is a Sight for Sore Eyes Scientific Calculator Boils Down to Two ICs $100 BOM Eludes First OLPC Laptop 45 nm: What Intel Didn't Tell You Next Step in NAND Flash Evolution Surveillance on a Shoestring Hot 3G Phone Owes Debt to Analog SecurID Fob: Single-Chip Safety Net

Under the Hood - June 23, 2008

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