EE Times Under the Hood - June 23, 2008 - (Page U60)

UTH0623SEMI_pg58_68.qxd 6/10/08 4:15 PM Page 60 under the hood: w w w. e e t i m e s . c o m SEMI CONDUC TORS urement that would essentially run between the sidewall spacer on either side of the gate. However, because the barrier is quite thin, it cannot account for the gate measurement difference. What appears to set the electrically active gate length is the “bird’s beak” formed where the sidewall spacer meets the TIL. SI analysis concluded that this bird’s beak is the result of TIL and high-k etches undercutting the polysilicon. Reoxidation of the polysilicon sidewall prior to silicon nitride spacer formation exacerbates the undercut. For the metal gate deposited into the trench, there is a thick, relatively low-k path toward the channel at this point that clearly could not electrically influence charge carriers in the region underneath the bird’s beak. The critical portion of the metal gate could also be the TIL itself. Because this layer is composed of the same work-function metal as the gatelast layer, perhaps its edge defines the metal gate length. Fortunately, the edge of the TIL layer approximately aligns with the bird’s beak above it, so the choice of measurement point will not affect the value you get for LG. The punch line is that the gap between the gate trench edge and the electrically active edge of the workfunction metal (whether first or last) accounts for somewhere between 8 and 10 nm. And that appears to explain the difference between Intel’s reported value for LG and what the rest of us have been looking at. Despite its cure for leakage power, the addition of hafnium creates headaches for the process integration engineer. Intel avoided hafnium’s downsides (threshold voltage pinning and reduced carrier mobility) by creating a silicon oxide (or possibly oxynitride) bottom interface layer between the silicon substrate and the HfO2 layer. The bottom interface layer not only gets hafnium into the gate stack, it also gives the process engineer one more tuning knob. Because the gate dielectric’s influence on the transistor channel and electrical performance is a function of the individual contributions of the various layers, threshold voltages can be controlled by varying the thickness of this layer for different >>64 • w w w. t e c h o n l i n e . c o m deposited immediately after the hafnium oxide dielectric. Adding aluminum to form TiAlN tunes the work function for the n-channel transistors. Intel’s process protects HfO2 from the polysilicon etch by depositing the first work-function layers before forming and patterning polysilicon. Semiconductor Insights (SI) engineers refer to the first metal gate layer as the top interface layer (TIL) because of the undeniable protection it provides the HfO2 dielectric. The p-type metal gates are TiN, and Al is added to create TiAlN and the appropriate work function for NMOS. Thicker layers of both metals are deposited in their respective n- and p-channel transistors after removing the sacrificial polysilicon, and a barrier layer is formed on the bottom and sidewalls of the trench left behind by the polysilicon etch. Debates about the meaning of “gate” are arguably less important than the electrical performance of the finished product. Intel’s 45-nm technology is certainly impressive in that regard. At 1 volt at room temperature, SI’s extraction of transistor electrical parameters indicates a saturated drive current (IDSAT) of 1.08 mA/micrometer for the PFET and 1.36 mA/μm for the NFET. Intel confirmed these values at its IEDM presentation (although our PFET number is actually 10 μA higher than Intel reported). Not surprisingly, our results show higher drive currents at low temperature (–20°C) and reduced current at high temperature (85°C). These high values for drive current provoke more questions regarding the gate structure. There has always been a discrepancy between the physical gate length (LG) of transistors and the shorter electrically active channel length (Lelec). Before the advent of modern metal gate technology, however, it was relatively easy to specify LG and compare transistor performance among fabs. The Intel gate structure creates some new problems for analysts. Intel reports a gate length of 35 nm, which fits well with the 1.36-mA/μm drive current generated by its NFET. But the edge-to-edge dimension of the gate structure is closer to 45 nm if measured in a fashion similar to the IN BRIEF Intel’s 45-nm process technology incorporates high-k hafniumbased dielectric material, titanium nitride for the PFET replacement gate and a TiN barrier alloyed with a work-function tuning metal for the NFET replacement gate. Intel uses a gate-last, or replacement gate, process flow, and it’s whether it’s “gate” or “last” in reference to the polysilicon deposition that is scrutinized.This replacement gate flow allows Intel to reuse process steps and tools from polysilicon-gate technology, leveraging self-aligned processes for source and drain formation and lightly doped extension regions. SI discovered that the first work-function metal is deposited prior to the gate polysilicon. High values for the saturated drive currents of the technology prompted SI to question the gate structure, as the ratios of the drive currents and the source/drain extension lengths would be out of whack to produce the high values determined. The location of the metal gate’s edge and the use of a barrier material explain the discrepancy. standard used for polysilicon gates. So what gives? The ratios of LG, Lelec and source/drain extension lengths would be out of whack to produce such large saturation currents. The answer appears to be related to our question about the location of the metal gate’s edge. In the past, it was assumed that the entire width of the poly gate influenced carriers in the transistor channel. Because polysilicon is etched and replaced with a metal gate filling the trench in the gate-last process, the situation is less straightforward. The first material deposited into the gate trench is not metal for the gate, but actually a barrier material. This means the active portion of the gate is less than the traditional length meas- 60 Electronic Engineering Times, TechOnline | June 23, 2008 http://www.techonline.com http://www.eetimes.com

Table of Contents Feed for the Digital Edition of Under the Hood - June 23, 2008

Under the Hood - June 23, 2008 Extreme Design: SuitSat Pushes Desigers' Limits Evolution of the Smart Phone Mature Devices get Rolly Rocking GPS: Garmin Nuvi 750 vs. HP iPaq 310 Inside the Sony OLED TV Multizone Dgital Audio Flip Ultra Camcorder - An Ode to Clean Design Robot Guitar Tunes Itself E-book is a Sight for Sore Eyes Scientific Calculator Boils Down to Two ICs $100 BOM Eludes First OLPC Laptop 45 nm: What Intel Didn't Tell You Next Step in NAND Flash Evolution Surveillance on a Shoestring Hot 3G Phone Owes Debt to Analog SecurID Fob: Single-Chip Safety Net

Under the Hood - June 23, 2008

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