EE Times Under the Hood - June 23, 2008 - (Page U62)

UTH0623SEMI_pg58_68.qxd 6/10/08 4:15 PM Page 62 under the hood: w w w. e e t i m e s . c o m SEMI CONDUC TORS • w w w. t e c h o n l i n e . c o m Designers boost DRAM efficiency BY YOUNG CHOI ith less than the highest possible operating frequency (1.6 GHz) and a steep price premium, DDR3 DRAM made little progress last year, as buyers opted instead for performance-enhanced DDR2 parts. Responding to harsh DRAM market conditions, suppliers are now offering more-efficient designs for both the mainstream DDR2 market and the nextgeneration DDR3 market. W According to research house DRAMeXchange, the overall DRAM market was extremely tough throughout 2007, burdened by less-than-ideal demand and excess capacity from new plants. These factors caused DRAM prices to fall below variable cost at one point in the fourth quarter. The average price of 512-Mbyte, 667-MHz DDR2 devices fell 55 percent in 2007, compared with 2006. When industry sources revealed that even a DRAM maker operating with 12-inch facilities on a 70-nanometer process would still come out at a loss, this losing proposition sped up the retiring of 8-inch facilities from the production of commodity DRAM. Semiconductor Insights (SI) reported DDR3 analysis results based on some of the early products of Micron, Qimonda and Samsung. According to the analyses, published last May and September, the overhead of enhanced speed and low power consumption of DDR3 over DDR2 was between 22 and 23 percent in the 90-nm and 80-nm process nodes. A comparison can be made based on Samsung and Qimonda DRAM data with 80-nm and 90-nm processes, respectively. Cell efficiency for DDR3 designs ranges from 33 percent to 45 percent, but cell efficiency for DDR2 designs of the same process technology is much higher (from 41 percent to 54 percent). A wide internal data bus and its related circuitry, including data read/write amplifier and multiplexing circuits to support an 8-bit prefetch architecture, consume precious silicon area. Contributing to this die size overhead are extra pipeline stages to support high-speed I/O operations, improved on-die termination circuitry and other features introduced in the DDR3 standard. One DRAM manufacturer’s reaction to this situation is noteworthy. The latest Micron DDR3 DRAM analyzed by SI shows the smallest DDR3 chip size around—one very comparable to that of DDR2. The area overhead of DDR3 compared with DDR2 has almost disappeared in Micron’s 78-nm, 1-Gbyte 6F2 DDR3 DRAM (with x8 organization). Industry sources say this particular design has been optimized for x8 and x4 only. By removing x16 options, Micron’s design appears to have Die photo of Micron DDR3—SI# 19770 DRAM market transition Die photo of Micron DDR2—SI# 19769 Die photo of Hynix DDR2—SI# 19359 Chip size overhead of DDR3 over DDR2 (relative comparison) 2000 2001 2002 2003 2004 2005 2006 2007 2008 2009 2010 2011 Introduction DDR1 Volume transition 90 nm 80 nm DDR2 DDR3 DDR1 DDR2 DDR3 Device density Chip size Gross dice per wafer DDR2 DDR3 DDR2 DDR3 1 1 1.22 0.81 1 1 1.23 0.82 SDRAM Source: Samsung Tech Forum, November 2007 Source: Semiconductor Insights 62 Electronic Engineering Times, TechOnline | June 23, 2008 http://www.eetimes.com http://www.techonline.com

Table of Contents Feed for the Digital Edition of Under the Hood - June 23, 2008

Under the Hood - June 23, 2008 Extreme Design: SuitSat Pushes Desigers' Limits Evolution of the Smart Phone Mature Devices get Rolly Rocking GPS: Garmin Nuvi 750 vs. HP iPaq 310 Inside the Sony OLED TV Multizone Dgital Audio Flip Ultra Camcorder - An Ode to Clean Design Robot Guitar Tunes Itself E-book is a Sight for Sore Eyes Scientific Calculator Boils Down to Two ICs $100 BOM Eludes First OLPC Laptop 45 nm: What Intel Didn't Tell You Next Step in NAND Flash Evolution Surveillance on a Shoestring Hot 3G Phone Owes Debt to Analog SecurID Fob: Single-Chip Safety Net

Under the Hood - June 23, 2008

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