EE Times Under the Hood - June 23, 2008 - (Page U64)

UTH0623SEMI_pg58_68.qxd 6/10/08 4:15 PM Page 64 under the hood: w w w. e e t i m e s . c o m SEMI CONDUC TORS • w w w. t e c h o n l i n e . c o m achieved die area parity with DDR2. This is an important development in the DRAM market, which expects to make the DDR2-to-DDR3 transition sometime between 2009 and 2010. Another notable change in Micron’s latest designs is a pronounced similarity across the board. As companies gain more experience working with DDR3 designs, designers are finding ways to reuse many design blocks and techniques to reduce development cost, ease device analysis and produce more-efficient designs. Micron, for example, used two very similar floor plans in its latest 78-nm DDR2 and DDR3 devices. Research shows that the 6F2-cell-based DRAM is roughly 13 percent smaller in chip size than the 8F2, and that it is accompanied by about a 15 percent increase in the number of gross dice per 12-inch wafer. Although the 6F2 cell advantage of 25 percent less area is reduced somewhat to get 15 percent more dice per wafer, this increase in the number of gross dice is pivotal in maintaining the profitability and competitiveness of DRAM manufacturers. Traditionally, Micron has used its 6F2-cell-based DRAM successfully. Samsung has been using its 6F2 cell in the 90-nm and 68-nm process nodes. In the DRAM market—in which prices have dropped more than 50 percent in a year—Qimonda’s new road map to 6F2-cell-based and even 4F2-cell-based DRAM products is hardly surprising. One exception One DRAM manufacturer stands out as an exception to this trend: Hynix. As the second-biggest manufacturer in the worldwide DRAM market, how does Hynix’s technology compare with Samsung’s and Micron’s more-efficient 6F2-cell-based DRAM technologies? Recent analysis conducted by SI on two comparable DRAM devices from Samsung and Hynix might shed some light on this question. According to the analysis, Hynix’s 66-nm, 1-Gbyte DRAM (128-Mbyte x8) is an impressive design, with a die area only 4 percent larger and a 4 percent lower gross number of dice per 8-inch wafer. This is a major improvement over its 80-nm, 512-Mbyte DRAM design, which suffered a 15 percent reduction in the IN BRIEF DDR3 designs have matured, and Micron appears to have achieved DDR3 die area parity with DDR2.Also observed from Micron’s recent DDR3 and DDR2 analysis was the evidence of design reuse between DDR2 and DDR3: architecture, floor plan, etc. Hynix’s latest DDR2 shows how more-aggressive process scaling with smart DRAM array architecture, periphery designs could help a company without 6F2 technology compete against those with 6F2. It’s been shown that 8F2 cell DRAM could potentially be as efficient as 6F2 cell DRAM given more relaxed DRAM cell design rules, larger cell capacitance, more-compact and -efficient folded bitline-based DRAM array design (as opposed to lower-efficiency open-bitlinebased DRAM array with 6F2 cell), provided that the design is highly optimized in both the array and the periphery. number of gross dice per 8-inch wafer compared with Samsung’s 80-nm, 512Mbyte 6F2-cell DRAM design. Hynix’s lack of a 6F2-based cell must have forced the company to pursue more-aggressive process node scaling (66 nm, as apposed to Samsung’s 68 nm) and to rely on innovative design and layout. Judging from a chip-size and gross-dice perspective, SI believes this design to be very competitive with comparable designs from both Samsung and Micron. Aggressive scaling, combined with clever design and layout, the reuse of circuit blocks and architectures, and the optimization of certain features to develop more-efficient DRAM products, will be important for the survival of manufacturers in today’s harsh commodity DRAM market. These efforts will accelerate the market’s transition from current DDR2 to nextgeneration DDR3, expected in the next year or two. ■ <<60 45 NM transistor apps. Process variability, and designing for it, is a hot topic as factors such as line-edge roughness and random dopant fluctuations become more problematic at 45 nm. Intel addressed this in a second IEDM presentation, in which Intel fellow Kelin J. Kuhn, director of logic device technology, discussed improving yield via process improvements and design changes. The SRAM cell illustrated Kuhn’s point as she showed the evolution from 90-nm to 45-nm design. The “tall” cell layout used at 90 nm was replaced with a “wide” cell at 65 nm. The 65-nm cell design improved dimension control and variability by aligning the polysilicon in a single direction and removing the corners in the active area patterns. At 45 nm, Intel’s process removed “dog bone” and “icicle” shapes by employing only square end caps. These uniform structures are also easier to fill reliably in the gate-last process. Intel continues to use 193-nm dry lithography at 45 nm. Restricted design rules create “structured” gate layouts. This design-for-manufacturability technique of uniform, regular arrangement of metal gates improves yields for the advanced HKMG technology without requiring new immersion tooling. Creating strictly rectangular gate patterns did require an extra step, because double-patterning was used for the sacrificial polysilicon layer. Many features of Intel’s 65-nm process remain in evolved forms. The new process uses “thirdgeneration” strained silicon that is structurally similar to the embedded silicon germanium PMOS of Intel’s 65-nm process. Nickel salicide is also used again at 45 nm. Intel employs dualdamascene copper up to metal nine. A SiCN barrier with carbondoped oxide creates the low-k interlevel dielectric integration scheme. ■ 64 Electronic Engineering Times, TechOnline | June 23, 2008 http://www.eetimes.com http://www.techonline.com

Table of Contents Feed for the Digital Edition of Under the Hood - June 23, 2008

Under the Hood - June 23, 2008 Extreme Design: SuitSat Pushes Desigers' Limits Evolution of the Smart Phone Mature Devices get Rolly Rocking GPS: Garmin Nuvi 750 vs. HP iPaq 310 Inside the Sony OLED TV Multizone Dgital Audio Flip Ultra Camcorder - An Ode to Clean Design Robot Guitar Tunes Itself E-book is a Sight for Sore Eyes Scientific Calculator Boils Down to Two ICs $100 BOM Eludes First OLPC Laptop 45 nm: What Intel Didn't Tell You Next Step in NAND Flash Evolution Surveillance on a Shoestring Hot 3G Phone Owes Debt to Analog SecurID Fob: Single-Chip Safety Net

Under the Hood - June 23, 2008

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