EE Times Under the Hood - June 23, 2008 - (Page U66)

UTH0623SEMI_pg58_68.qxd 6/11/08 4:13 PM Page 66 under the hood: w w w. e e t i m e s . c o m SEMI CONDUC TORS • w w w. t e c h o n l i n e . c o m Next steps in NAND flash evolution s 40-nanometer NAND flash products are prepared for mass production, and as technologies emerge to achieve densities beyond 2 bits per cell (multilevel-cell technology), with 3- and 4-bit/cell technology in sight, reviewing the first four generations of NAND flash technologies can provide a clearer view of the how the industry might evolve over the next few years. BY YOUNG CHOI A NAND flash, because of its smaller cell size and nonvolatile data storage, has become the storage device of choice for many consumer electronic devices, especially portable and handheld applications. The driving force behind the ubiquitous application and use of NAND flash devices is the continuous innovation in the process technologies and design techniques used to implement larger NAND flash devices with reduced production cost. This article examines the latest trends in NAND flash process nodes, cell types, chip sizes and cell sizes from a device technology standpoint. Fifteen NAND flash devices from five manufacturers (Samsung, Toshiba/SanDisk, Hynix, STMicro, Process node comparison of NAND flash and DRAM Product code Toshiba/SanDisk IMFT (Micron) Samsung Toshiba Toshiba Hynix Samsung Toshiba/SanDisk IMFT (Micron) Samsung Samsung Hynix Samsung Toshiba/SanDisk ST Samsung Hynix Density MLC/SLC Process node ISSCC 2008 data MT29F16G08MAAWP K9GAG08U0M-PCB00 TC58NVG4D1DTG00 TC58NVG3D1DTGI0 HY27UT088G2M K9G8G08U0M TC58NVG3D4CTG00 MT29F4G08AABWP K9F4G08U0A K9G4G08U0A HY27UF084G2M K9F4G08U0M TH58NVG3D4BTG10 NAND04GW32AN1 K9G4G08U0M HY27UH088G2M 16G 16G 16G 16G 8G 8G 8G 8G 4G 4G 4G 4G 4G 4G 4G 4G 2G MLC MLC MLC MLC MLC MLC MLC MLC SLC SLC MLC SLC SLC MLC MLC MLC SLC 43 nm 50 nm 51 nm 56 nm 56 nm 60 nm 65 nm 70 nm 50 nm 65 nm 65 nm 70 nm 73 nm 90 nm 90 nm 90 nm 90 nm Source: Semiconductor Insights and Intel/Micron) have been analyzed. Detailed structural and circuit analyses of the select devices conducted by Semiconductor Insights are the basis of this article. The analysis focuses on the latest NAND devices, ranging from 2-Gbit singlelevel cell (SLC) to 16-Gbit MLC types. All NAND flash devices analyzed in this article are based on floating-gate technology. The accompanying table lists the NAND flash devices that were examined. The devices are sorted according to process node. (Note that Toshiba/SanDisk’s 43-nm NAND flash information is sourced from ISSCC 2008 data.) The list covers major NAND flash devices introduced from late 2005 to 2008 and includes both SLC and MLC products. Process nodes range from 90 nm for early products in 2- and 4-Gbit densities to the latest, 43-nm products at 16 Gbits. The latest NAND flash devices commercially available as of January 2008 are manufactured in 50-nmgrade technologies that include 50, 51 and 56 nm. IM Flash Technologies (IMFT; a joint venture of Intel and Micron) is the leader in terms of minimum feature process size, at 50 nm. Toshiba/SanDisk manufactures MLC products in 56-nm process technology with immersion lithography. The minimum feature size of Samsung’s latest 16-Gbit MLC NAND flash is 51 nm. Meanwhile, 50-nm process technologies from Toshiba/SanDisk and Samsung introduced in 2007 have been essential to maintaining competitiveness in a climate of rapidly declining NAND flash prices. In February, Toshiba/SanDisk announced a 16-Gbit MLC NAND flash device manufactured in 43-nm 66 Electronic Engineering Times, TechOnline | June 23, 2008 http://www.eetimes.com http://www.techonline.com

Table of Contents Feed for the Digital Edition of Under the Hood - June 23, 2008

Under the Hood - June 23, 2008 Extreme Design: SuitSat Pushes Desigers' Limits Evolution of the Smart Phone Mature Devices get Rolly Rocking GPS: Garmin Nuvi 750 vs. HP iPaq 310 Inside the Sony OLED TV Multizone Dgital Audio Flip Ultra Camcorder - An Ode to Clean Design Robot Guitar Tunes Itself E-book is a Sight for Sore Eyes Scientific Calculator Boils Down to Two ICs $100 BOM Eludes First OLPC Laptop 45 nm: What Intel Didn't Tell You Next Step in NAND Flash Evolution Surveillance on a Shoestring Hot 3G Phone Owes Debt to Analog SecurID Fob: Single-Chip Safety Net

Under the Hood - June 23, 2008

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