EE Times Under the Hood - June 23, 2008 - (Page U68)

UTH0623SEMI_pg58_68.qxd 6/11/08 4:13 PM Page 68 under the hood: w w w. e e t i m e s . c o m SEMI CONDUC TORS • w w w. t e c h o n l i n e . c o m or eight times the minimum feature size square (6F2 or 8F2), NAND flash technologies have a smaller cell-size multiplier because of the simpler structure of the NAND flash cell. This is another reason why NAND flash technology has advanced ahead of DRAM. Based on the NAND flash process trends observed by this analysis, NAND flash devices are generally one lithography generation ahead of DRAM devices. For example, the latest commercially available flash devices are in the range of 50 to 56 nm, but DRAM devices are available in the range of 66 to 68 nm (50-nm process node DRAM devices have been reported, but have not been able to be confirmed at the time of this writing). Key findings of this analysis are that: • MLC technology, combined with advanced lithography, has been the driving force behind the widespread use of NAND flash devices. • MLC technology at 50 nm has achieved 100-Mbit/mm2 bit density. • The NAND flash industry made the transition from 70-nm, 8-Gbit to 50-nm, 16-Gbit technology in 2007. • Both 16-Gbit and 32-Gbit NAND flash devices in 40-nm MLC technologies are expected within the year. • NAND flash process nodes are generally one generation ahead of DRAM process nodes. NAND overtook DRAM as the process lithography leader approximately 18 months ago. • Greater bit density is sought via 3- or 4-bit/cell technology or, in some cases, three-dimensional stacking. • Upon the advent of 3- or 4bit/cell technology, the role and importance of NAND flash controllers are expected to increase in order to compensate for complex read/write algorithms and higher ECC requirements. • New applications, such as solidstate disks, have emerged as market segments for the NAND flash industry, bringing with them reduced production costs, diminished power consumption, improved reliability and stepped-up performance. ■ process technology (the most advanced MLC NAND flash device to date). The previous generations of NAND flash devices range from 60 nm and 65 nm to 70 nm and 73 nm. These technologies were adopted to produce 4- and 8-Gbit SLC/MLC NAND flash devices in 2006 and 2007, and a 90-nm process node was widely used for 2- and 4-Gbit MLC devices between 2004 and 2006. By means of advanced process technology, NAND flash density has been continuously increased from 2 Gbits at the 90-nm node to 16 Gbits at 43 nm. Despite the increase in density, the chip size of NAND flash devices has ranged from 130 mm2 to 170 mm2 until the 43-nm process node. The latest 16-Gbit MLC NAND flash announced by Toshiba/SanDisk achieved an impressive die size of 120 mm2. That opens the door to 12inch-wafer processing capabilities for cost-effective manufacture of 32-Gbit MLC NAND. NAND flash cell sizes have been continuously reduced as process technologies have advanced. The current, 50-nm process node is close to 0.01 square micrometer, almost 3.5 times smaller than the most advanced DRAM cell size examined by Semiconductor Insights. The simple structure and layout of NAND flash cells (based on a 4F2 cell cell design) help achieve the smallest possible cell design with whatever process technology is used. The NAND flash industry has continued to improve lithography to define smaller geometry and achieve smaller cell sizes. Despite some technical challenges, the current 43-nm process technology has achieved 40 percent smaller cell sizes than were achieved using the previous, 56-nm process node. NAND flash cell sizes, expressed in terms of multiples of minimum feature size square (F2), show the trend. Most of the NAND flash devices analyzed in this research have cell sizes close to four times the minimum feature size square within the acceptable statistical margin of error. Compared with DRAM technologies, in which cell sizes are either six Based on observed trends, NAND flash is generally one lithography generation ahead of DRAM. 68 Electronic Engineering Times, TechOnline | June 23, 2008 http://www.eetimes.com http://www.techonline.com

Table of Contents Feed for the Digital Edition of Under the Hood - June 23, 2008

Under the Hood - June 23, 2008 Extreme Design: SuitSat Pushes Desigers' Limits Evolution of the Smart Phone Mature Devices get Rolly Rocking GPS: Garmin Nuvi 750 vs. HP iPaq 310 Inside the Sony OLED TV Multizone Dgital Audio Flip Ultra Camcorder - An Ode to Clean Design Robot Guitar Tunes Itself E-book is a Sight for Sore Eyes Scientific Calculator Boils Down to Two ICs $100 BOM Eludes First OLPC Laptop 45 nm: What Intel Didn't Tell You Next Step in NAND Flash Evolution Surveillance on a Shoestring Hot 3G Phone Owes Debt to Analog SecurID Fob: Single-Chip Safety Net

Under the Hood - June 23, 2008

For optimal viewing of this digital publication, please enable JavaScript and then refresh the page. If you would like to try to load the digital publication without using Flash Player detection, please click here.