EE Times Under The Hood - October 8, 2007 - (Page 66) under the hood: SEMICONDUCTORS capacitor. The DDR3 device uses a spherical recess-access transistor with a gate length of 47 nm. The wordline width and pitch are 47 μm and 165 nm, respectively. The bitline width and pitch are 40 nm and 160 nm. Micron DDR3 The Micron 1-Gbit DDR3 sample’s die size is 102 mm2, and it has 38 percent cell efficiency. Micron’s 6F2 cell, with an area of 0.0365 μm2, is the smallest DRAM cell SI has analyzed. It appears that use of copper interconnect for metal 2 and metal 3, combined with a smaller cell size, helped Micron designers achieve desired performance with 1-Gbit DDR3 design. Despite there being a long distance for signals to travel in the larger die, relatively low resistivity and a lowprofile copper interconnect helped reduce signal resistor-capacitor (RC) delay as well as power consumption. Compared with Micron’s 110-nm, 512-Mbit DDR2 design, the main wordline lengths appear to have been halved in the 1-Gbit DDR3 design. Relatively short main wordlines and the use of copper data lines are merits for DDR3 operation, especially for lower latency and higher speed. Micron uses a 6F2 cell design with a MIM capacitor and a recessed-channel access transistor. The wordline width and pitch are 63 nm and 156 nm, respectively. The bitline width is 80 nm—the same as Samsung’s. The bitline pitch is 156 nm, slightly smaller than Samsung’s 160 nm. The 6F2 cell implementation reduces the Micron die’s chip size by 24 percent, compared with Samsung’s. Each DDR3 SDRAM www.eetimes.com • www.techonline.com design shows distinguishing features: Micron’s uses a single row of bonding pads, while Samsung’s uses two rows. Data bus manipulation and pipeline handling appear to take place in the periphery area of Micron’s design. Samsung, however, has these operations performed by distributing them across the memory array area. Comparison of DDR2 and DDR3 Currently, DDR3 SDRAMs cost two to three times as much as DDR2 SDRAMs. SI’s analyses of DDR2 and DDR3 designs from multiple manufacturers show that the typical DDR3 chip size premium over DDR2 is between 22 and 23 percent. That translates to about 20 percent fewer gross dice per given wafer. For example, a 300-mm wafer generating 90nm devices can yield about 950 DDR2 gross dice. DDR3 design would result in only 770 gross dice with the same 90-nm technology. The cell efficiency for DDR3 designs ranges from 33 to 45 percent, whereas the efficiency for DDR2 designs is much higher, between 41 and 54 percent. The wide internal data bus and related circuitry, including data read/write amplifier and multiplexing circuits to support 8-bit prefetch architecture, consume precious silicon area. Extra pipeline stages to support DDR3’s high-speed I/O, improved on-die termination circuitry and other features contribute to the die size overhead. Given DDR3’s relatively low cell efficiency, higher-density DDR3 designs (1 Gbit and higher) make the most sense. High-volume sales of DDR3 SDRAMs are not expected until mid2009, when DDR3 is predicted to reach price parity with DDR2. Those announced so far can perform up to 1,066 MHz, comparable to the performance of high-end DDR2 SDRAMs. But for the market to justify a switch to DDR3, devices with 1,033MHz or even 1,600-MHz performance would be required. Components for the highest-speed, 1,600-MHz versions will become available when manufacturers transition to 70- and 6-nm DRAM geometries, which is expected between 2008 and 2009. ■ 66 Electronic Engineering Times, TechOnline | October 8, 2007 http://www.eetimes.com http://www.techonline.com
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