Conformity Magazine - January 2009 - (Page 24) There are several key factors that are critical for successful susceptibility scanning: • A board or system being scanned needs to be monitored in order to determine that a circuit has been upset, and this can be done in several ways including: ° ° ° ° Controlled noise bursts, such as the electrical fast transient commonly used for system level testing RF (but then what frequencies should be used?) ° Voltage probing suspect nodes or traces Monitoring of data streams looking for errors Optical monitoring of status indicators • Testing a device requires specific input circuitry and careful monitoring of the outputs: ° • The test level needs to be carefully selected. It would be desirable to select a level equivalent of that which would result from a system level test or from field failures, but determining that level can be extremely complex. However, it is imperative that the level selected not cause circuit damage. Unlike other testing done to determine ESD withstand levels of devices, susceptibility scanning is, by definition, non-destructive. Putting Everything Together Device manufacturers already do considerable testing to ensure that devices can withstand relatively high ESD voltages and remain operational (that is, without damage), but the levels at which upset or malfunction might occur are unknown. Even the additional testing of devices to system level standards (IEC 61000-4-2, for example) still doesn’t provide any information about sensitivity to upset. EMC susceptibility scanning on devices operating on a test board or in a known circuit configuration solves this problem. Devices can be qualified in a way that helps a manufacturer ensure passing system level compliance tests, and which provides useful, and previously unavailable, information to the device manufacturer regarding the device performance. For the system level manufacturer currently doing EMC compliance testing, an ESD event causes upset, but there’s no information about what happened and hence the guess work begins (what circuits are involved, let’s try some ferrites, let’s see if a different case material will help, etc.). EMC scanning at the system level will quickly pin down the sensitive area(s) in a design, telling the engineer where to focus his attention, and saving both time and money. Now the system level manufacturer can go to the device people with a test that makes sense and not just another of looking at the voltage withstand levels. Hence, the new EMC testing dynamic, as shown in Figure 4. A Word About ESD Events Why should one believe that finding the sensitive areas of a board or circuit will ensure passing system level tests and Testing of a complex device is typically done in a known system or sub-system where the device can be properly exercised, and its effect on the system monitored. Generic device testing of a complex IC is a practical nightmare. It will typically require considerable circuitry to get it into a known state, exercise its functions and monitor its outputs. ° • Selection of the noise source can be critical to determining a circuits’ response. There are many possible noise sources, including: ° ° A fast, ESD like pulse A square wave with defined rise and fall times Figure 3: A diagram illustrating the critical components of an automated EMC immunity scanner 2 Conformity JAnUAry 2009
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