Conformity Magazine - June 2008 - (Page 34)

is changed to separate out a single power and a single ground pin to provide quiet power to a small but critical circuit, the number of stresses increases to 4680 (2340 positive and 2340 negative). Today many integrated circuits have 40 or 50 or more separate power supply groups. The result is 10s or 100s of thousands of individual stresses and many hours of test time. Long test time has been addressed in the standards by reducing the number of stresses from 3 to 1, and by reducing the delay between stresses from 1 second to 0.3 seconds and even 0.1 seconds in the latest JEDEC standard. Long test time remains an issue. Wear Out The intent of HBM testing is to ensure that an integrated circuit can survive the manufacturing process. Once the integrated circuit is within a completed system, the system should provide ESD protection. All electronic manufacturing is done in ESD controlled areas to reduce the number and severity of ESD events. Without ESD controls, even products that can survive 2000V of HBM stress would not survive manufacture. An integrated circuit, in its entire lifetime, is not expected to experience more than a handful of ESD events of modest severity. HBM testing, in its attempt at thoroughness, exposes the circuit to many more stresses than a circuit will experience in a typical lifetime. Each of the HBM stresses does exercise a unique current path, but parts of paths will be stressed repeatedly. It is well known in the ESD community that wearout is an issue, but there is almost nothing in the literature documenting it formally. Stress Count Reduction Excessive test time and wear-out are technically different issues, but the solutions are often related. Wear out is often dealt with by dividing testing between a number of samples. Rather than doing all pin combinations on each sample, subsets of the pin combinations are done on separate samples. This procedure increases the amount of handling during testing, but can significantly reduce the number of stresses individual samples experience. Test time is obviously not improved and more samples are needed for testing. Dividing the pin combinations across a number of samples can also be very useful in the case of failure, since the pin combinations that could have caused a failure are greatly reduced. A recent change in the JEDEC HBM standard has had a beneficial impact on both test time and wear-out. Most very high pin count integrated circuits are packaged in ball grid array (BGA) packages. BGA packages are typically made on a circuit board-like substrate, with many separate interconnect layers. Power pin groups with multiple balls are usually shorted together with a power plane on one of the BGA’s layers. When this is done the resistance between different pins in the same power pin group is very low. Stressing any single pin within the power pin group should be equivalent to stressing any of the other pins. Figure 1: Basic HBM Schematic. S1 initiates the stress pulse and S2 is used to remove built up charge after the stress through a high resistance. Figure 2: Measured HBM waveform for 2000V into a short Pin Combination 1 2 i n n+1 Grounded Pins Supply Group 1 Supply Group 2 Supply Group i Supply Group n All I/O except stressed I/O Stress Pins All pins not grounded, one at a time All pins not grounded, one at a time All pins not grounded, one at a time All pins not grounded, one at a time Each I/O pin, one at a time Floating Pins All pins not in Supply Group 1 and not under test All pins not in Supply Group 2 and not under test All pins not in Supply Group i and not under test All pins not in Supply Group n and not under test All Supply Pins Table 1: Pin Combinations for HBM testing for an integrated circuit with n power supply groups 34 Conformity JUnE 2008

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Conformity - June 2008 Contents Editor's Note 700 MHz Auction Raises a Record $20 Billion FCC Modifies PCS and AWS Power Limit Rules for Broadband Wireless Commission Designates Spectrum Test Bed FCC Releases Report on Wireless Competition Commission Proposes $5 Million Fine for Slamming Using EDX for Non-Destructive Detection of Lead in Consumer Products ESD Open Forum Challenges in Testing - Improving Election Security and Accuracy Part 1 Challenges in Testing - Human Body Model: The Hidden Challenges High-Speed Signal Integrity Considerations for ESD Components Focus On...EMC Components Buyer's Guide FCC Levies $2.6 Million Fine for Junk Faxes FDA Updates Guidance on its Product Review Process EU Issues Updated Energy Star Regulations EU Repeals Directive on Veterinary Electro-Medical Equipment New Product Announcements Updated Standards List for the EU's PPE Directive CPSC Announces New Effort to Keep Out Hazardous Products CPSC Actions in the News IEC Standards Update UL Standards Update Product Reviews Telcordia Standards Update From Our "You Can't Make This Stuff Up" Department Looking Back: Items from Past Issues of Conformity Advertisers

Conformity - June 2008

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