Conformity Magazine - June 2008 - (Page 36)

Under these conditions the JEDEC HBM standard allows a single pin of a power pin group to represent the entire power pin group. This change can significantly reduce test time in some designs and also greatly reduce repetitive stressing to the device. Integrated circuits that do not have a package power plane cannot use this technique because on the die metal connections can amount to several Ohms of resistance, making different pins within the power pin group not identical. A method that has been proposed that would reduce both test time and wear-out is the partitioned HBM test.[3] This method significantly modifies the pin combinations as presented in Table 1. Testing is divided up into three partitions, with separate samples for each of the partitions. The intra-domain partition stresses all pins within power domains, but does no stressing between power domains. The inter-domain partition stresses all power and ground pins with respect to each other. The final partition stresses each signal pin against all other signal pins. In the partition method, signal pins are never stressed with respect to power pin groups that do not supply the signal pin buffers. Users of this method report that circuits with high numbers of power domains have similar failure levels as circuits with fewer power domains, indicating less wear-out. It is also reported that the method is very effective at indicating the location of ESD weak circuits. The method cannot, however, be considered in full compliance with the HBM standards at this time. Trailing Pulse Several years ago, Texas Instruments traced a subtle degradation from ESD stress to small currents that flowed into the device under test from the HBM simulator many microseconds after the HBM current pulse.[4] The currents only affected advanced technologies with thin gate oxides, and were only present in some HBM simulator models. The currents were traced to ionized gas in the relay S1 in Figure 1. The ionized gas provided a current path between the high voltage power supply and the device under test. Since then, the HBM standards have added a test to detect the presence of this current, and pulse source upgrades have become available for some HBM simulators that exhibited the problem. [1] The standards have not required that all HBM simulators remove the current because many IC technologies are not affected by the current. For advanced CMOS technologies, it is important to determine if the HBM simulator being used is free from the trailing current. Pre Pulse Voltage In the same period that the trailing pulse was discovered, another HBM simulator effect was discovered, the pre pulse voltage. [5] During an investigation of unexpected failures of ESD power supply protection circuits, it was discovered that several volts could build up across a device under test if the pin combination had high impedance and low capacitance. Under these conditions, some dynamic power supply clamps did not turn on. (The pre pulse voltage will be the subject of a future article in Conformity and will not be discussed further here.) HBM Simulator Parasitics Figure 3: Conceptual schematic of relay matrix based automated HBM simulator HBM stressing of integrated circuits with hundreds of pins can not be done without automated test equipment. A conceptual schematic of a relay matrix HBM simulator is shown in Figure 3. Automated HBM simulators allow a stress pulse to be applied to any pin on the circuit and for one or more pins to be connected to the ground terminal, while the remaining pins remain floating. Not shown in Figure 3 are the circuits and relays needed to accommodate the leakage measurements circuitry present in most automated HBM simulators. Automated HBM simulators have been extremely successful at allowing HBM stressing to be done on high pin count circuits in an efficient and reliable manner. Occasional reports, however, indicated that in some cases interactions between the automated simulators and the circuit under test resulted in unexpected results. [6] This led to the ESDA HBM working group, WG5.1, to investigate the behavior of a number of commonly used automated HBM simulators.[7] The method used was to employ special shorting modules that would short Figure 4: Measurement of input and output waveforms with a short module 36 Conformity JUnE 2008

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Conformity - June 2008 Contents Editor's Note 700 MHz Auction Raises a Record $20 Billion FCC Modifies PCS and AWS Power Limit Rules for Broadband Wireless Commission Designates Spectrum Test Bed FCC Releases Report on Wireless Competition Commission Proposes $5 Million Fine for Slamming Using EDX for Non-Destructive Detection of Lead in Consumer Products ESD Open Forum Challenges in Testing - Improving Election Security and Accuracy Part 1 Challenges in Testing - Human Body Model: The Hidden Challenges High-Speed Signal Integrity Considerations for ESD Components Focus On...EMC Components Buyer's Guide FCC Levies $2.6 Million Fine for Junk Faxes FDA Updates Guidance on its Product Review Process EU Issues Updated Energy Star Regulations EU Repeals Directive on Veterinary Electro-Medical Equipment New Product Announcements Updated Standards List for the EU's PPE Directive CPSC Announces New Effort to Keep Out Hazardous Products CPSC Actions in the News IEC Standards Update UL Standards Update Product Reviews Telcordia Standards Update From Our "You Can't Make This Stuff Up" Department Looking Back: Items from Past Issues of Conformity Advertisers

Conformity - June 2008

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