Conformity Magazine - June 2008 - (Page 39)

small increase in the peak current on the A Side. The increased peak current is due to the low high frequency impedance of the parasitic paths. The peak current measured on the B side is significantly reduced and there is a large increase in the rise time. Current through the parasitic path is very large until the relay matrix capacitance is charged. The parasitic current then reverses sign as the relay matrix capacitors discharge. How an integrated circuit is affected by simulator parasitics will vary from circuit to circuit. Circuits that are damaged by peak current may exhibit a higher HBM passing level, due to the simulator parasitics. Protection strategies that rely on a fast transient to turn protection circuits on may not work as intended during HBM testing. [6] A recent study by one equipment manufacturer has shown how simple spacers inserted between the test board and the simulator’s relay matrix can greatly reduce parasitic effects. [9] The same study also showed that, at least for some circuits, the A side current pulse is more important than the B side pulse in determining device failure. It is important to note that no field failures have been linked to improper testing due to simulator parasitics. HBM Qualification Levels For many years 2000V has been the generally accepted value for passing the HBM ESD test. In recent years, with advanced integrated circuit technologies with smaller feature size, it has become more difficult to reach 2000V HBM. The result has been costly redesigns and delays in the introduction of new products. During the same period the ability to control ESD events in the manufacturing process has made the handling of products with HBM levels even below 500V routine. The Industry Council on ESD Target Levels was formed in 2006 to determine the ESD robustness needed in today’s manufacturing environment. The council is made up of ESD experts from a broad cross section of integrated circuit manufacturers, test system manufacturers and other interested parties. In 2007 the council released a white paper recommending that a 1000V HBM level was more than adequate to ensure that electrical components can survive the manufacturing process. [10] Summary The migration of HBM testing to more advance integrated circuits has not been without its challenges. Integrated circuit advances required the development of automated HBM simulators, allowing the testing of complex circuits. Over the years, problems such as the trailing pulse and pre pulse voltage have prompted modifications to some of the test systems. Today, the industry struggles with excessive test time, wear out and unintended interactions between the test system and the device being tested. Despite this, HBM remains a positive force in the electronics industry, preventing costly yield loss during manufacture. Robert Ashton is a senior protection and compliance specialist at ON Semiconductor, and can be reached at Robert.Ashton@onsemi.com. References 1. JEDEC, “JESD22-A-114D, Electrostatic Discharge (ESD) Sensitivity Testing Human Body Model (HBM) Component Level,” 2006 2. ESD Association, “Standard Test Method for Electrostatic Discharge (ESD) Sensitivity Testing: Human Body Model (HBM) Component Level,” 2000. 3. R. Gaertner, R. Aburano(1), T. Brodbeck, H. Gossner, J. Schaafhausen, W. Stadler, F. Zaengl, “Partitioned HBM Test - A New Method To Perform HBM Tests On Complex Devices”, EOS/ESD Symposium 2005, p 178. 4. C. Duvvury et. al., “Gate Oxide Failures Due to Anomalous Stress from HBM ESD Testers,” EOS/ESD Symposium, 2004, p 132. 5. R. Ashton and E. Worley, “Pre Pulse Voltage in the Human Body Model,” EOS/ESD Symposium, 2006, p 326. 6. H. Kunz, “The Effect of High Pin-Count ESD Tester Parasitics on Transiently Triggered ESD Clamps,” EOS/ESD Symposium, 2004, p 146. 7. M. Chaine et.al., “HBM Tester Parasitic Effects on High Pin Count Devices with Multiple Power and Ground Pins,” EOS/ESD Symposium, 2006, p 354. 8. K. Verhaege et.al., “Analysis of HBM ESD Testers and Specifications Using a 4th Order Lumped Element Model”, EOS/ESD Symposium, 1993, p 129. 9. R. Given et.al., “Sudy of the Impact of Non-selected I/O Pins during HBM Test using ZapMaster Mk.2”, September 2007, www.conformity.com/1851. 10. Industry Council on ESD Target Levels, “White Paper 1: A Case for Lowering Component Level HBM/MM ESD Specifications and Requirements,” www.esdtargets.blogspot.com. FAST Link www.conformity.com/1850 JUnE 2008 Conformity 39 http://www.conformity.com/1851 http://www.esdtargets.blogspot.com http://www.conformity.com/1850

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Conformity - June 2008 Contents Editor's Note 700 MHz Auction Raises a Record $20 Billion FCC Modifies PCS and AWS Power Limit Rules for Broadband Wireless Commission Designates Spectrum Test Bed FCC Releases Report on Wireless Competition Commission Proposes $5 Million Fine for Slamming Using EDX for Non-Destructive Detection of Lead in Consumer Products ESD Open Forum Challenges in Testing - Improving Election Security and Accuracy Part 1 Challenges in Testing - Human Body Model: The Hidden Challenges High-Speed Signal Integrity Considerations for ESD Components Focus On...EMC Components Buyer's Guide FCC Levies $2.6 Million Fine for Junk Faxes FDA Updates Guidance on its Product Review Process EU Issues Updated Energy Star Regulations EU Repeals Directive on Veterinary Electro-Medical Equipment New Product Announcements Updated Standards List for the EU's PPE Directive CPSC Announces New Effort to Keep Out Hazardous Products CPSC Actions in the News IEC Standards Update UL Standards Update Product Reviews Telcordia Standards Update From Our "You Can't Make This Stuff Up" Department Looking Back: Items from Past Issues of Conformity Advertisers

Conformity - June 2008

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