Conformity Magazine - June 2008 - (Page 41)

aintaining good signal integrity while providing adequate electrostatic discharge (ESD) protection at a system level is increasingly challenging. Interface speeds for digital consumer electronics and personal computers are rapidly increasing. HDMI, DisplayPort, and eSATA are already running at multi-gigabit/sec data rates, and other ports such as USB are expected to continue the trend within the next year. These higher speed circuits are usually implemented in the latest semiconductor manufacturing geometries, which are more vulnerable to ESD damage. Semiconductor devices are predicted to become increasingly prone to ESD damage as these geometries continue to shrink,1 increasing the need for robust ESD protection external to the transmitter and receiver chips. Integrated circuit manufacturers have continued to decrease the minimum dimensions of the transistors, interconnections, and the SiO2 insulation layers in their devices. This results in smaller structures for higher speed devices which are more susceptible to electrical overstress (EOS) breakdown damage at lower energy levels. SiO2 layers are more likely to rupture and metal traces are more likely to open or bridge during an ESD event. High speed receivers and transmitters will usually include some on-chip ESD circuits to provide protection within a controlled manufacturing environment, but a typical realworld ESD event can deliver a peak current of over 30 Amps, and enough I2R heating to permanently destroy the relatively small input clamps in a deep sub-micron receiver or transmitter IC. Therefore, system designers must use external ESD protection devices to ensure adequate system reliability. Unfortunately, ESD protection devices and associated design techniques that were successfully used for slower speed ports such as USB 2.0 (480 Mbps) are inadequate for these higher data rates. There are several challenges confronting a design engineer trying to provide excellent signal integrity with adequate ESD protection: M • Pin-compatible parts can often vary widely from vendor to vendor, and in some cases lot to lot, which can lead to signal integrity problems in the field even if a system appears to work well in the lab. Complicating these issues are other manufacturing constraints that are often placed on the design engineer. For example, consumer electronics manufacturers often use several PCB board vendors. The board vendors can have different board stack-up parameters such as dielectric thickness, which makes it difficult for engineers to do an impedance controlled layout that is portable from vendor to vendor. While these challenges appear daunting, by carefully selecting ESD components and applying good design techniques, it is possible to provide excellent ESD protection while simultaneously maintaining excellent signal integrity at multigigabit data rates. Capacitance Specifications Most engineers understand that, as data rates increase, they need to select lower capacitance ESD devices to minimize signal attenuation (see Figure 1). Generally, for these data rates, it is recommended that capacitance be kept below 1.5 pF2, although in practice it is better to choose even lower capacitance devices, provided they can achieve sufficient levels of protection. • Retaining good signal integrity suggests minimizing shunt parasitics, such as stray capacitance; • As the capacitance of an ESD protection circuit goes down, the EOS shunt power capacity is reduced and the protection level tends to degrade. Lower capacitance usually means higher clamping voltages and higher residual current into the protected ASIC, both of which contribute to ESD damage; capacitance matching, pinout and routing options become much more important than at lower data rates; misleading information regarding key product parameters; JUnE 2008 Conformity 41 • At these high speeds, seemingly secondary issues such as • ESD product datasheets can sometimes list confusing or http://www.ddbunlimited.com http://www.ddbunlimited.com

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Conformity - June 2008 Contents Editor's Note 700 MHz Auction Raises a Record $20 Billion FCC Modifies PCS and AWS Power Limit Rules for Broadband Wireless Commission Designates Spectrum Test Bed FCC Releases Report on Wireless Competition Commission Proposes $5 Million Fine for Slamming Using EDX for Non-Destructive Detection of Lead in Consumer Products ESD Open Forum Challenges in Testing - Improving Election Security and Accuracy Part 1 Challenges in Testing - Human Body Model: The Hidden Challenges High-Speed Signal Integrity Considerations for ESD Components Focus On...EMC Components Buyer's Guide FCC Levies $2.6 Million Fine for Junk Faxes FDA Updates Guidance on its Product Review Process EU Issues Updated Energy Star Regulations EU Repeals Directive on Veterinary Electro-Medical Equipment New Product Announcements Updated Standards List for the EU's PPE Directive CPSC Announces New Effort to Keep Out Hazardous Products CPSC Actions in the News IEC Standards Update UL Standards Update Product Reviews Telcordia Standards Update From Our "You Can't Make This Stuff Up" Department Looking Back: Items from Past Issues of Conformity Advertisers

Conformity - June 2008

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