Conformity Magazine - June 2008 - (Page 46)

A simple method for understanding the signal integrity on a transmission line is to look at the impedance along that line. The goal of a designer is to provide matched differential impedance along the line to minimize reflections and signal attenuation. A common method for determining the characteristic differential impedance of a transmission line is called time domain reflectometry (TDR). A TDR plot shows the differential impedance of the transmission line along the signal traces. As capacitance is added to a line (such as when adding an ESD diode to an HDMI signal path), the characteristic impedance of that line will drop. Table 1 shows the relative effects of a very small change of capacitance relative to the change in differential impedance. These results were obtained by using two ESD devices in identical footprints on the same board. The board was designed with 100 ohm differential traces, and the TDR was measured with a rise time of 200 ps. No compensation was done to offset the effects of the diode capacitance on these boards. The results show that even a small difference in capacitance can have a dramatic impact on the impedance of the transmission line. In this case, even the lower capacitance Capacitance ESD Clamp A ESD Clamp B 0.53pF 0.75pF Minimum Impedance 94 Ohms 90 Ohms Discontinuity Deviance -6 Ohms -10 Ohms device caused a 6 ohm drop in impedance, and increasing the capacitance by a mere 0.22 pF caused an additional 4 Ohm drop. While both of these designs are well within the compliance limits for specifications such as HDMI 1.3 and DisplayPort 1.1a, they illustrate how even small variations in capacitance can dramatically impact the transmission line impedance and thus the signal integrity. As an additional consideration, not only do system designers need to compensate for the parasitic capacitance of the ESD device, but they also need to take into account part to part variations, and even board to board variations. Therefore, it is important to minimize impedance mismatches caused by the design itself. Luckily, there are several methods for reducing the effects of capacitance on the characteristic differential impedance of a signal line. These controlled impedance design techniques are well-known to designers of communications equipment, which has been operating in multi-gigabit data rates for years. In contrast, most PC and digital consumer electronics designers have only faced these design challenges recently and may not be familiar with these techniques. Common design practices include: • Reducing board-level capacitance in the region of the ESD device; • Increasing trace inductance in the region of the device; • Adding inductance, such as a choke, to the line near the ESD device. All of these techniques have advantages as well as limitations. The characteristic impedance at any point along the transmission line is a function of the square root of the unit characteristic inductance divided by the unit characteristic capacitance (see Equation 1). In other words, increasing capacitance causes the impedance to drop, while increasing the inductance causes the impedance to increase. Therefore, to offset the capacitance of an ESD device, the designer needs to reduce capacitance elsewhere in the vicinity of the ESD device or increase the inductance in that area. Zo = Table 1: Comparing two capacitance levels on 100 ohm uncompensated differential traces Figure 6: Traditional routing for 2-channel ESD device (ground connection not shown) √ Lo Co Reducing Board Level Capacitance This can be done by increasing the dielectric spacing to the ground plane under the trace, either by ordering a different PCB composition from the vendor, or by omitting an intermediate layer, i.e. Layer 3 GND + Layer 1 Signal, instead of L2+L1. Depending on the PCB board stackup, this can reduce the magnitude of discontinuities due to Figure 7: Routing using impedance matched ESD devices (ground connection not shown) 46 Conformity JUnE 2008

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Conformity - June 2008 Contents Editor's Note 700 MHz Auction Raises a Record $20 Billion FCC Modifies PCS and AWS Power Limit Rules for Broadband Wireless Commission Designates Spectrum Test Bed FCC Releases Report on Wireless Competition Commission Proposes $5 Million Fine for Slamming Using EDX for Non-Destructive Detection of Lead in Consumer Products ESD Open Forum Challenges in Testing - Improving Election Security and Accuracy Part 1 Challenges in Testing - Human Body Model: The Hidden Challenges High-Speed Signal Integrity Considerations for ESD Components Focus On...EMC Components Buyer's Guide FCC Levies $2.6 Million Fine for Junk Faxes FDA Updates Guidance on its Product Review Process EU Issues Updated Energy Star Regulations EU Repeals Directive on Veterinary Electro-Medical Equipment New Product Announcements Updated Standards List for the EU's PPE Directive CPSC Announces New Effort to Keep Out Hazardous Products CPSC Actions in the News IEC Standards Update UL Standards Update Product Reviews Telcordia Standards Update From Our "You Can't Make This Stuff Up" Department Looking Back: Items from Past Issues of Conformity Advertisers

Conformity - June 2008

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