Conformity Magazine - September 2008 - (Page 33)

In the original PPV paper [3] two physical mechanisms were proposed that might explain the PPV. The first was that, as the relay closed, gas in the relay would start to ionize, but not enough to trigger the full scale avalanche that creates the HBM current pulse. The ionization current could charge the capacitance of the DUT and parasitic capacitance of the HBM simulator, creating the observed PPV. The second proposal was that the relay S1 represents a variable capacitance as it closes. A schematic for this model is shown in Figure 4. (The capacitor CDUT includes not only the DUT capacitance but also parasitic capacitance in the HBM simulator.) The model assumes a starting condition with the 100pF CHBM capacitor charged to the HBM voltage. Voltage across the DUT is assumed to be 0V. The relay S1 is open with the relay elements far apart, such that the relay capacitance, CS1, is low. Under these conditions, the voltage across CS1 must be equal to the HBM voltage. As the relay closes, the relay elements get closer together and the capacitance CS1 increases. As the capacitance increases, more charge is needed to maintain the HBM voltage across the relay. On one side, the charge must come from the 100pF capacitor, slightly lowering the voltage across CHBM. On the other side the charge must come from the DUT. For very large values of RDUT, some of the charge must come from CDUT. This increases the voltage across CDUT, resulting in a PPV. Measurements by Barth et. al. [4] using vacuum relays, which are not subject to the ionization mechanism, proved that the PPV was caused by capacitance change within the relay as it closed. Dynamic ESD Clamps and PPV A sample dynamic ESD clamp, often called a BigFET, is shown in Figure 5. The clamp is placed between power and ground. With steering diodes to power and ground on inputs and outputs, and an ESD diode between VDD and VSS, the BigFET can provide a full HBM protection strategy. In its on state, the BigFET’s large nMOS can conduct the full HBM current pulse without damage, and maintain the VDD to VSS voltage within a safe range. The inverter chain and RC circuit are designed to keep the large nMOS off during normal operation, but turn on the large nMOS during an ESD event. While power is applied to the circuit, node A in Figure 5 is held high and, due to the three stages of inverter, node B will be held low, keeping the large nMOS device off. The HBM ESD test is intended to determine an integrated circuit’s ESD robustness before it is inserted on a circuit board. The HBM test is therefore performed on an unpowered integrated circuit. Consider a positive ESD event on VDD with respect to VSS. The rapid rise of VDD versus VSS caused by the ESD event will result in node A staying close to VSS for an RC time constant. With node A held low, the three stages of inverters will hold node B high, turning on the large nMOS device, providing a safe path for the HBM current stress. ESD stresses that result in negative stress between VDD and VSS are handled by forward biased diodes, typically formed by nWell to substrate diodes. Dynamic clamps have two main advantages. They protect without relying on avalanche breakdown, and their behavior can be predicted using Spice simulation. The failure of dynamic clamps to function due to the PPV on low leakage circuits is easy to explain. The PPV develops while the relay S1 in Figure 1 is closing, which takes many µs Figure 1: Basic HBM schematic showing the location of the device under test, the positioning of the Zener diode and Zener diode with parallel resistors as well as the location of the voltage probe during measurement of the PPV Low-Profile Gaskets 125LP45, 125LP55 & 125LP60 "Smooth to the Touch" Low closing force Adhesive mounting Bi-directional Gap range - .030" - .130" Durable with 360° No-snag 100db attenuation Also available with Hook-on mounting for additional mechanical security Optional DiamondBack (dB) texture for high frequencies Beryllium Copper Immediate delivery MOUNTING SURFACE Low Profile LowProfile PRESSURE SENSITIVE ADHESIVE .03" MIN. INSERTION Free Samples at www.tech-etch.com/shield ISO 9001:2000 REGISTERED TECH-ETCH, INC., 45 Aldrin Road, Plymouth, MA 02360 September 2008 Conformity 33 http://www.tech-etch.com/shield

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Conformity Magazine - September 2008 Contents Editor’s Note Commission Adopts Regulations for Internet-Based TRS Services Another Company Fined for Non-Compliance with HAC Requirements FCC Extends “Do-Not-Call” Registry Compliance Requirements Marketing Company Gets $1.4 Million Fine for Junk Faxes EU Commission Codifies Directive on TTE Market Competition EU Commission Releases Updated Standards List for the R&TTE Directive Updated Standards List for the “New” Low Voltage Directive Released New Standards List Released for the EU’s Machinery Directive The ESD Association: Voluntary Standards in Action ESD Open Forum Medical EMC Standards: Towards the 4th Edition of IEC 60601-1-2 iNARTE Informer Pre-Pulse Voltage in the HBM ESD Model Digital Interfaces and EMC Performance ESD Design Buyer’s Guide Product News Commission Publishes Updated Standards List for the EU’s Personal Protective Equipment Directive FDA Links “Human Factors” to Adverse Events with Medical Devices CPSC Actions in the News IEC Standards Update UL Standards Update Product Reviews Telcordia Standards Update From Our “You Can’t Make This Stuff Up” Department Looking Back: Items from Past Issues of Conformity Advertisers

Conformity Magazine - September 2008

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