Conformity Magazine - December 2008 - (Page 16)

Required ESD Levels for Devices Integrated circuits (IC) are tested for ESD robustness using one or more of the three device-level ESD tests, HBM, CDM, and machine model (MM). These tests are intended to ensure that the circuits can survive the manufacturing process. Which tests are performed and the passing level required is usually set between the manufacturer and purchaser of the circuit. The most commonly required passing voltages are 2000V for HBM, 500V for CDM and 200V for MM. As integrated circuit technologies have advanced and performance demands have increased, it has become increasingly difficult to meet these passing levels. In many instances, exceptions to these passing levels have been allowed. Experience has shown that the lower passing level product did not have higher failure levels if basic ESD control procedures were employed during their manufacture. IC customers, however, have continued to request the commonly accepted ESD voltage levels, under the impression that higher levels must be better. The effort to meet the commonly accepted ESD passing levels costs considerable money due to redesign and product delays. The Industry Council on ESD Target Levels was formed to determine what level of ESD robustness is required to survive the manufacturing process, and to recommend safe but realistic ESD target levels. It is a group of experts representing major IC manufacturers, contract manufacturers (CMs), ESD tester manufacturers, ESD consultants and ESD IP companies. Setting realistic goals will save money by not requiring unnecessary redesigns, thereby improving time to market without compromising yields in the manufacturing process. The Council’s first project was the release of a white paper on HBM and MM testing.[1] This document showed considerable data on the failure rates during manufacture for ICs with different levels of HBM and MM passing voltages. Based on this data, the Council recommended an HBM passing level of 1000V HBM. The Council also recommended a de-emphasis on MM testing. The Council’s data indicated that ICs that pass 1000 V HBM will have at least 30 V MM robustness, but could have MM robustness much higher than that. The data also showed 30 V of MM robustness was sufficient for high yield in a quality manufacturing environment. The Industry Council is currently educating the electronics industry about their recommendations for HBM and MM, and the advantages for both IC suppliers and OEMs if more reasonable ESD target levels were adopted. The Council is beginning to have success, and it is anticipated that 1000V HBM will soon become the generally accepted value for HBM testing. As the industry becomes comfortable with this level, and as integrated circuit technologies continue to advance and performance goals increase, it is likely that even 500 V will become a commonly accepted value for HBM acceptance. 1 Conformity DeCember 2008 The second activity of the Industry Council is the development of a white paper on recommended CDM target levels. This is likely to be a bigger challenge than the white paper on HBM and MM, since CDM testing is more challenging. There are several CDM test methods that produce different failure levels. Additionally, the size of the IC changes the stress experienced during a CDM event. It is anticipated the Council will need to make a recommendation that goes beyond adjusting the commonly accepted passing level to a new voltage. Human Body Model (HBM) HBM is the most mature of the device-level ESD test methods. As we discussed in a previous article (see Conformity, June 2008), there are still areas that present challenges for HBM testing. [2] The joint standards development effort between JEDEC and ESDA is currently addressing the HBM standard. At present, an ad hoc committee from both groups is addressing the technical issues where the two standards differ, and will shortly start to draft the joint standard. That joint document will not be a major issue for the industry. There will likely be small changes in calibration procedure and other procedural changes, but there will not be a change in the pass/fail levels when the new document is adopted. The two test methods never differed in significant ways and a harmonization effort was undertaken several years ago. Some of the more challenging aspects of HBM testing will not be addressed by the joint committee until a merged document is available. Modern high pin count products with a large number of independent power and ground pin groups employed to reduce noise present a challenge in testing. Test times increase dramatically, and current paths are stressed hundreds or thousands of times, leading to wear-out. HBM is intended to ensure that an integrated circuit can survive at most a handful of ESD stresses during manufacture. The challenge is to ensure that there are no weak pin combinations, without excessive test times and wear-out. There are several methods that can be used to address excessive test times and wear-out. There is a provision in the JEDEC test method, but not in the ESDA method, that can be used to at least partially address both the wear-out and test time issues. If an IC uses power planes within a package to short all of the pins within a power or ground group together, a single pin may be chosen to represent the stress on the entire group. This will be an area of potential interest when the joint ESDA/JEDEC standard is issued. Another method that could be used to deal with the long test times and wear-out issues is to modify the pin combinations in HBM. Modifications of HBM pin combinations have been discussed in the available literature [3], and it is expected that there will be considerable deliberation on this approach in future standards development efforts.

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Conformity Magazine - December 2008 Contents Editor's Note FCC Warns Regulatory Fee Payers About Potential "Phishing" Commission Prowls the Web to Enforce Its Regulations First DTV Rollout Initiated in Wilmington, NC New Standards List Released for the EU's Directive on the Safety of Toys ESD Association Call for Papers ESDA. JEDEC Announce Standards Development Cooperation Commission Releases Data on Local Telephone Competition The Future of ESD Testing ESD Open Forum Emerging Issues in Standards: China RoHS: One Year and Counting Challenges in Testing: Revisiting 10-Meter and 3-Meter Radiated Emission Measurements Design Fundamentals: Meeting the Shielding Challenges of Injection-Molded Plastics Focus On...Microwave Absorbers Buyer's Guide FDA Recalls Automated External Defibrillators FDA Revises Guidance on Medical Device Tracking Guidance Document Safety of Passive Implants Released FDA Offers Guidance on Marketing Diagnostic Ultrasound Systems EU Commission Issues Correction on Machinery Directive Standards Other CPSC Actions in the News Product Reviews IEC Standards Update UL Standards Update Looking Back: Items from Past Issues of Conformity Advertisers

Conformity Magazine - December 2008

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