Conformity Magazine - December 2008 - (Page 18)

discussed in [2]. The failures occur because the interaction between the tester and the device creates a stress quite different from the intended HBM stress. To date, it has required extensive engineering effort and judgment to resolve the problem. After extensive work, the debate has often been, did the IC pass the test? The obvious answer to this dilemma is to build new HBM testers that remove the parasitics. This is both obvious and, we believe, unlikely, since the current generation of relay matrixbased HBM test systems are, in general, serving the industry well. In most situations, the test results are as expected, or can be explained without invoking tester issues. The relay matrix systems are fast, which is a necessary feature with the high pin count devices that are increasingly being produced. There are currently no low parasitic tester ideas that have the speed needed to address the issues of modern high pin count ICs. We anticipate that failures due to tester parasitic issues will continue to be addressed on a case-by-case basis for the foreseeable future. We anticipate that standards bodies will provide some guidance on acceptable alternative pin combinations to reduce the problems due to tester parasitics. Charged Device Mode (CDM) CDM is a test method that may see considerable change over the next few years. The details of field-induced CDM (FCDM) are covered in [4]. The joint standards effort between JEDEC and ESDA will be part of this change. The two test methods are conceptually identical but differ in significant details. The insulator thickness between the device under test and the field plate is different, the test modules to calibrate the systems are different, and there are differences in the required waveforms. The result is that ICs tested according to both standards do not receive the same passing voltage levels. The ESDA test method is usually considered the more severe stress, resulting in lower passing voltages. Merging the test methods will be a challenge when there is often no clear cut technical advantage of one method over the other. Complicating this is that the merged test method will likely produce a change in the passing voltage when users move to the new standard. Maintaining dual standards is not, however, a good long term practice for the industry. As discussed above, the Industry Council on ESD Target Levels is now focusing on CDM. Their recommendation, and the industry’s reaction to the recommendation, will greatly influence the future of CDM testing. Their recommendation may significantly change how CDM data is viewed and interpreted. A change in how product is qualified is usually met with considerable reluctance and this may be no exception. The good news is that any recommendation by the Council will be backed by considerable real world manufacturing data, as was their recommendation for HBM. There are also some basic concerns about the field-induced CDM method used in both the JEDEC and ESDA test methods. FCDM uses an air discharge to initiate the stress. Air discharge can vary considerably, and atmospheric conditions such as temperature, humidity and pressure all affect the test results. The shape and cleanliness of the probe tip that initiates the air discharge between the test head and the device under test also has a significant effect on the size of the stress current pulse. These factors combine to produce a wide scatter in the stress current, resulting in more variability in the test results than is considered acceptable by many test engineers. There is considerable interest in an arc free CDM test which maintains the speed of the current FCDM test method. An alternative method for producing a CDM speed current pulse without an air discharge, as well as without a relay that will slow the pulse shape, is capacitively coupled transmission line pulse (CC-TLP). The basic concept is shown in Figure 2. An IC is placed pin side up on top of a thin insulator on a grounded metal field plate. A coaxial probe touches the pin to be tested. A voltage pulse, produced by a very fast transmission line pulse system, will inject a current pulse dependent not only on the properties of the voltage pulse but also proportional to the capacitance between the IC and the field plate. A number of papers have been published on this subject. A CDM tester based on this technique would remove the problems inherent in an air discharge test method, and should be relatively straightforward to automate. Test time with an automated system of this type should be similar to those for Figure 2: Capacitively coupled TLP, simplified test setup, stress voltage for 50 Ω load, and current into integrated circuit during cc-TLP 18 Conformity DeCember 2008

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Conformity Magazine - December 2008 Contents Editor's Note FCC Warns Regulatory Fee Payers About Potential "Phishing" Commission Prowls the Web to Enforce Its Regulations First DTV Rollout Initiated in Wilmington, NC New Standards List Released for the EU's Directive on the Safety of Toys ESD Association Call for Papers ESDA. JEDEC Announce Standards Development Cooperation Commission Releases Data on Local Telephone Competition The Future of ESD Testing ESD Open Forum Emerging Issues in Standards: China RoHS: One Year and Counting Challenges in Testing: Revisiting 10-Meter and 3-Meter Radiated Emission Measurements Design Fundamentals: Meeting the Shielding Challenges of Injection-Molded Plastics Focus On...Microwave Absorbers Buyer's Guide FDA Recalls Automated External Defibrillators FDA Revises Guidance on Medical Device Tracking Guidance Document Safety of Passive Implants Released FDA Offers Guidance on Marketing Diagnostic Ultrasound Systems EU Commission Issues Correction on Machinery Directive Standards Other CPSC Actions in the News Product Reviews IEC Standards Update UL Standards Update Looking Back: Items from Past Issues of Conformity Advertisers

Conformity Magazine - December 2008

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