EETimes India - September 1-15, 2008 - (Page 10)

In Focus | Board-level Test Get the low down on IEEE 1588 clock synchronisation continued from page • • • Establishing orderly startup and reconfiguration of the system; Providing the necessary information to allow slave clocks to correctly synchronise to their master; and Providing system and clock management capability when needed by an application. System boundaries PTP is designed to operate on packet-based networks that support multicast communications. There are five message types defined by PTP: 1. Sync; 2. Delay Req; 3. Follow Up; 4. Delay Resp; 5. management. Message types Sync and Delay Req are called “event messages,” since they are used as timing events by the PTP protocol. Message types Follow Up, Delay Resp, and management are called “general messages”. Follow Up and Delay Resp messages are used to convey timing information. Both event and general messages are to be communicated using a multicast model of communication to enable the self- configuration objective of the standard to be met. Management messages are normally communicated using a multicast model, but in addition are permitted to use a point-to-point model. Figure 1 shows a typical IEEE 1588 system topology that allows independent synchronisation systems to be maintained on the same communication network. Each system maintains its time scale independently of the others. These independent synchronisation systems are called “subdomains.” Subdomains are implemented by defining a namespace, so that each subdomain is distinguished by a subdomain name. All PTP messages contain the name of the applicable subdomain. All interactions, communications, and other features of IEEE 1588 occur within a single subdomain, and are logically independent of similar operations in other subdomains. Performance impairments There may be performance impairments that result from multiple subdomains sharing a common communication fabric. These impairments result from communication or processor loading on system components. The boundary of a subdomain is determined by the underlying communication fabric and how it responds to multicast messages. The PTP protocol will synchronise all clocks in a subdomain that receive and process PTP event and general messages. Therefore, to limit the extent of an IEEE 1588 subdomain, it is necessary to correctly limit the propagation of multicast messages in the underlying communication fabric. This may be done physically by isolating the subdomain, or logically by proper configuration of routers, switches and similar network equipment. A system such as Figure 1 above typically contains several end or terminal devices, and several network devices. An end device is a device with only a single network connection. End devices containing a PTP clock are termed “ordinary clocks” in the standard. Read the full article to learn more about network components with specialised IEEE 1588 functionality and much more. Online | Implement real-time systems using IEEE 1588 IEEE 8 02.15.4/ ZigB e e for b ug - f re e systems Combine techniques to reduce ICT cost, complexity continued from page has been inserted into the chain of boundary-scan devices. A “cluster” of three nonboundary-scan devices is surrounded by three boundaryscan devices. The boundaryscan registers in U1, U2 and U3 can be used to drive test-pattern stimuli into the non-boundaryscan cluster, and to observe the cluster responses. Generation of the test is again automatic, which is a good thing, considering that these tests can sometimes go up to 1 million lines—which can potentially make the debug very complicated for a more complex IC. Hybrid tech Wouldn’t it be ideal to be able to test what VTEP is capable of testing today—including connectors and sockets—without the need for physical test ac- cess? Incidentally, these connectors and sockets represent a large chunk of nodes on a board with their sheer number of pins. A typical notebook architecture analysis suggests this to be around 600 nodes. With the overview of VTEP and boundary-scan in mind, let us take a look at how a hybridisation of these two technologies result in Cover-Extend Technology, which essentially does away with the need for test access (Figure 1). Here’s how it works: 1. The VTEP sensor, which is able to capacitatively pick up stimulus signals, is placed on the component to be tested (e.g. a connector). 2. Traditional VTEP methodology required physical test access (i.e. test probes) to deliver this stimulus signal. However, with Cover-Extend, 3. 4. 5. 6. the stimulus signal is delivered via a boundary-scan device. The boundary-scan device does not require test probes on every pin. As per the IEEE 1149.x standard, using only the test access port, users can deliver the necessary stimulus signal to the connector. A defect (e.g. an open) on the path between the boundary scan device and the VTEP sensor will affect the stimulus signal that is bound for the sensor. The result is captured and diagnosed by the ICT system and thus the defect is detected! access, there comes significant savings in operational cost for fixturing and ICT test resources. For instance, you can now save on cost of test probes and associated costs such as wiring and maintenance on test fixtures. Also, you can minimise your need for ICT pin cards required to test your PCBs, thereby reducing the tester resources. This preserves users’ investment in ICTs. Cover-Extend can recover up to 50 per cent node access. Read the full article to learn more about how this hybrid technology puts less strain on sensitive ICs and its other benefits. Online | Cost reduction The implications are profound. First, let’s look at the cost of test. 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Table of Contents Feed for the Digital Edition of EETimes India - September 1-15, 2008

EETimes India - September 1-15, 2008 Contents National Semiconductor Get the Low Down on IEEE 1588 Clock Synchronisation Tech Insights DigiKey Combine Techniques to Reduce ICT Cost, Complexity Microchip Technology National Instruments SME, Educational Programmers Show How NI�Cares Texas Instruments

EETimes India - September 1-15, 2008

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