EETimes India - September 1-15, 2008 - (Page 6)

In Focus | Board-level Test Examine issues in serial bus debug continued from page • Wide availability of components using standard serial interfaces. While serial buses provide a number of advantages, they also pose some significant challenges to an embedded system designer due simply to the fact that information is being transmitted in a serial fashion rather than parallel. This article discusses common challenges for embedded system designers. complicate matters, the clock is embedded in the data and bit stuffing is used to ensure an adequate number of edges for the receiving device to lock to the clock. Faulty messages Even to the very trained eye, it would be extremely difficult to quickly interpret the content of this message. Imagine that this is a faulty message that only occurs once a day and you need to trigger on it. Traditional oscilloscopes and logic analysers are simply not well equipped to deal with this type of signal. Even with a simpler serial standard such as I2C, it is still significantly harder to observe what is being transmitted over the bus than it is with a parallel protocol. I2C uses separate clock and data lines, so at least in this case you can use the clock as a reference point. However, you still need to find the start of the message (data going low while the clock is high), manually inspect and write down the data value on every rising edge of the clock, and then organise the bits into the message structure. Parallel vs. serial With a parallel architecture, each component of the bus has its own signal path. There may be 16 address lines, 16 data lines, a clock line and various other control signals. Address or data values sent over the bus are transferred at the same time over all the parallel lines. This makes it relatively easy to trigger on the event of interest using either the state or pattern triggering found in most oscilloscopes and logic analysers. It also makes it easy to understand at a glance the data you capture on either the oscilloscope or logic analyser display. For example, in Figure 1, we’ve used a logic analyser to acquire the clock, address, data and control lines from an MCU. By using a state trigger, we’ve isolated the bus transfer we’re looking for. To “decode” what’s happening on the bus, all we have to do is look at the logical state of each of the address, data and control lines. With a serial bus, all this information must be sent serially on the same few conductors (sometimes one). This means that a single signal may include address, control, data and clock information. As an example, look at the CAN serial signal in Figure 2. This message contains a start of frame, an identifier (address), a data length code, data, CRC and end of frame as well as a few other control bits. To further Figure 1: Logic analyser acquisition of an MCU’s clock, address bus, data bus and control lines. Figure 2: One message acquired from a CAN bus. State, pattern triggers It can easily take a couple of minutes of work just to decode a single message in a long acquisition, and you have no idea if that’s the message you are actually looking for. If it’s not, then you need to start this tedious and error-prone process over on the next one. It would be nice to just trigger on the message content you are looking for, but the state and pattern triggers you’ve used for years on scopes and logic analysers won’t do you any good here. They are designed to look at a pattern occurring at the same time across multiple channels. To work on a serial bus, their trigger engines would need to be tens to hundreds of states deep (one state per bit). Even if this trigger capability existed, Figure 3: One message acquired from an I2C bus. it would not be a fun task programming it state-by-state for all these bits. There has to be a better way. Some oscilloscopes can now be used with some of the most common low-speed serial standards used in embed- ded system design to provide a better solution. Online | High-speed boards meet PCIe challenge Choosing the right data bus in industrial, automotive apps EE Times-India | September 1-15, 2008 | www.eetindia.com http://www.embeddeddesignindia.co.in/article/sendInquiry.do?articleId=8800541197&catId=2800005?ClickFromNewsletter_080901 http://www.embeddeddesignindia.co.in/article/emailToFriend.do?articleId=8800541197&catId=2800005?ClickFromNewsletter_080901 http://www.eetindia.co.in/article/email_friend.php3?article_id=8800515679&type=TA&cat_id=1800000&back_url=%2Farticle%2Farticle_content.php3%3Fin_param%3D8800515679_1800000_TA_427b9233%26 http://www.eetindia.co.in/ART_8800533338_1800004_TA_aa8d44bf.HTM?ClickFromNewsletter_080901 http://www.eetindia.co.in/ART_8800383958_1800006_TA_f6258b9a.HTM?ClickFromNewsletter_080901 http://www.eetindia.com/STATIC/REDIRECT/Newsletter_080901_EETI02.htm?ClickFromNewsletter_080901

Table of Contents Feed for the Digital Edition of EETimes India - September 1-15, 2008

EETimes India - September 1-15, 2008 Contents National Semiconductor Get the Low Down on IEEE 1588 Clock Synchronisation Tech Insights DigiKey Combine Techniques to Reduce ICT Cost, Complexity Microchip Technology National Instruments SME, Educational Programmers Show How NI�Cares Texas Instruments

EETimes India - September 1-15, 2008

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