EETimes India - October 8, 2008 - (Page 7) Trends PCIe expands interconnect potential for next-gen systems continued from page tions, from either a hardware or software perspective. An added economic benefit of the same PCIe switch being used on the line card and controller card is that purchasing/commodity teams have one less part on the bill of materials to deal with. For those few systems requiring more than 16 lanes and 16 ports, designers can take advantage of the two ports available on many processors to use two but rather handling all the controller functions on the same board the processor is built on. Here, the PCIe switch is connecting to a large number of end-points. Routing issues? In case of routing issues, two 8-lane, 8-port switches can be used (figure 4). With nearly all processors providing more than one PCIe port, this usage is possible without affecting latency Global PCIe interconnect market is expected to nearly quadruple, growing from Rs.237 crore in 2007 to Rs.839 crore in 2011. of the same devices to provide a total of 32 lanes 32 ports (figure 2). Two 16-lane, 16-port devices used on the controller card now provide a total of 30 lanes and 30 ports, and connect up to 30 line cards. This usage is possible because most available processors today provide dual-PCIe ports. Figure 3 shows a control plane on the same board—i.e. not going across a backplane or performance in the system. PCIe Gen1 interface (2.5Gbps) was introduced in 2003 and is the interface that currently appears on a large number of devices. PCIe Gen 2 interface (5Gbps) was introduced in 2007 and is beginning to replace Gen 1 interface in the market. Since the PCIe specification mandates that Gen 2 devices be backward-compatible with Figure 4: Two 8-lane, 8-port PCIe switches used instead of one 16-lane, 16-port switch. Figure 5: Gen 2 PCIe switch acting as a ‘bridge’ between Gen 1 and Gen 2 devices. Figure 2: System needing more than 16 lanes 16 ports. Figure 3: Control plane usage model on the same board. Gen 1 devices, in terms of lane speed (5Gbps versus 2.5Gbps, respectively) a Gen 2 PCIe switch can be used to future-proof systems which use current Gen 1 processors and a blend of Gen 2/Gen 1 end-points. Each port in a PCIe Gen 2 switch independently negotiates the functional link speed. A Gen 2 PCIe switch should be able to act as a “bridge” when there are Gen 1 devices in the system (figure 5). This “bridge” allows a mix of Gen 1 and Gen 2 devices and enables a system to operate at Gen 2 even though many components are Gen 1. It is expected that such usage models will continue to exist for sometime before the entire industry transitions to Gen 2 PCI Express. After years of spirited debate on the various interconnects to serve the worldwide markets for telecommunications, security and embedded systems, PCIe has come out on top. Nearly all processor vendors addressing these markets are offering PCIenative processors, with some expanding their product portfolio to include the Gen 2 PCIe interface in their products. Designers can expect that most, if not all, processor vendors will soon follow suit, which means that for systems being introduced in 2009 and beyond, a Gen 2 PCIe switch will be needed to build these next-generation systems. Meanwhile, PCIe switches from vendors are enabling versatile interconnect among these processors and the systems on which they are based. Online Solutions towards PCIe compliance and interoperability Use PCIe in multi-processor system configurations High-speed boards meet PCIe challenge 7 EE Times-India | October 1-15, 2008 | www.eetindia.com http://www.eetindia.co.in/ART_8800516339_1800000_TA_9373692b.HTM?ClickFromNewsletter_081001 http://www.eetindia.co.in/ART_8800539400_1800004_TA_6e25375e.HTM?ClickFromNewsletter_081001 http://www.eetindia.co.in/ART_8800533338_1800004_TA_aa8d44bf.HTM?ClickFromNewsletter_081001 http://www.eetindia.com/STATIC/REDIRECT/Newsletter_081001_EETI02.htm?ClickFromNewsletter_081001
Table of Contents Feed for the Digital Edition of EETimes India - October 8, 2008 EETimes India - October 8, 2008 National Semiconductor Tech Insights Trends Cadence Texas Instruments Fine-tuning RF Platform Shrinks Design Time DigiKey Mobile WiMAX Enables IP Convergence EETimes India - October 8, 2008 EETimes India - October 8, 2008 - EETimes India - October 8, 2008 (Page 1) EETimes India - October 8, 2008 - National Semiconductor (Page 2) EETimes India - October 8, 2008 - National Semiconductor (Page 3) EETimes India - October 8, 2008 - Tech Insights (Page 4) EETimes India - October 8, 2008 - Trends (Page 5) EETimes India - October 8, 2008 - Cadence (Page 6) EETimes India - October 8, 2008 - Cadence (Page 7) EETimes India - October 8, 2008 - Texas Instruments (Page 8) EETimes India - October 8, 2008 - Fine-tuning RF Platform Shrinks Design Time (Page 9) EETimes India - October 8, 2008 - DigiKey (Page 10) EETimes India - October 8, 2008 - DigiKey (Page 11) EETimes India - October 8, 2008 - Mobile WiMAX Enables IP Convergence (Page 12) EETimes India - October 8, 2008 - Mobile WiMAX Enables IP Convergence (Page 13) EETimes India - October 8, 2008 - Mobile WiMAX Enables IP Convergence (Page 14)
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