EETimes India - October 16, 2008 - (Page 10)

In Focus | Verification Environment eases reconfigurable design, verification continued from page Events WECON-2008 Oct. 18-19 Chitkara Institute of Engineering and Technology, Patiala processor has different native semantics compared to a fine grained FPGA). • Communication between the above two. Again, depending on the communication paradigm of the system, this has to be modelled by designers. However, at the early stages of system, designing a high level abstract model is suitable. A high-level co-simulation environment is needed to plug in all these disparate component models from different sources. Such an environment allows the designer to verify the complete system and perform hardwaresoftware co-design (if required). It also facilitates faster design space exploration, where the designer can make choices about the target reconfigurable platform. Figure 2 shows the concept of such an environment, where DF-SIM is the reconfigurable component, R-SIM is the RISC model, MEM is Memory model, and “synch” is the synchronisation module. The key challenge is to make different simulation models talk to one another in a synchronised manner. SystemC provides Transaction Level Modelling (TLM) capabilities, which can be used to abstract out various component models to higher level, and SystemC Clock Generator and Communication Channels, which can be used for synchronising various models. Such an abstract environment provides very fast system verification capability with relatively easy plug-and-play of components for design space exploration. The abstraction provided by SystemC TLM hides the lower level details of each component and can be used for plugging in even the hardware evaluation boards (instead of simulation models) in the cosimulation environment, without any change in user view and is useful for hardware-in-loop (HIL) verification. With such an environment at designers’ disposal, one can definitely expect higher designer productivity and shorter design and verification times. Online Ver i f i c ati o n I P reus e fo r co mp l e x networking ASICs Boost productivity with ESL techniques The International Conference on Wireless Networks & Embedded Systems hosts researchers, academics, and participants in the industry and R&D organisations to exchange information and experience on wireless networking and embedded systems. Download event brochure. Design houses will not survive shrinking margins SLN Murthy says, “The key differentiating factor that design houses in India should address is the need to provide a value proposition. There is still a lot of demand, but what we lack is trained manpower…” ICQMOIT-2008 Oct. 24-25 IBS, Dontanapalli, Hyderabad Figure 2: Co-simulation environment concept for a dynamically reconfigurable dataflow-based platform. The International Conference on Quantitative Methods, Operations and Information Technology focuses on addressing operational issues with quantitative methods and IT. Go to event website. Power India 2008 Nov. 6-8 Mumbai Grasp SystemVerilog testbench debug, analysis continued from page 9 hardware description languages (HDLs) are highly structured, and as such can be easily represented hierarchically in schematics or state diagrams. Not only are these contextually appropriate for the task at hand, but they also present information in a way that makes it possible for engineers to more easily comprehend. By contrast, software programs like SystemVerilog and C++ have classes that are created, instantiated, and extended everywhere. For engineers, especially those that come from the hardware domain, it is no easy feat to make sense of it all. Thus, the burden now falls on debug tools, which are tasked with inferring data and creating static views that are both useful and intuitive. Logging limitations The obvious next question is: how are these verification challenges being addressed today? Studies show that SystemVerilog is becoming a widely adopted element of verification (testbench) methodologies. Today, there are two primary strategies employed to help engineers comprehend, analyse and debug SystemVerilog testbench environments. Read the full article to know about these two strategies, and to find out how approaches borrowed from the software domain can be useful in testbench verification and debug, and more. | The event features exhibits from power plant and equipment, transmission and distribution, nuclear technology, environmental management, IT, instrumentation and automation, and consultancy segments. Get more details. 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Table of Contents Feed for the Digital Edition of EETimes India - October 16, 2008

EETimes India - October 16, 2008 Contents National Semiconductor Tech Insights Environment Eases Reconfigurable Design, Verification Texas Instruments Digikey Grasp SystemVerilog Testbench Debug, Analysis WELCON-2008, ICQMOIT-2008, Power India 2008

EETimes India - October 16, 2008

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