EETimes India - October 16, 2008 - (Page 3) Trends Tools manage verification data reports continued from page third party IP does come with its own environment and set of components, which may not be fully compatible with your existing environments. Mixedlanguage environments using dif ferent HVL, Verilog/ VHDL and other types of verification IP components add up to become one complex verification environment. Assigning verification tasks offshore is another practice that is becoming common because it reduces development costs. But when part of the verification team is twelve hours away, communicating the data back and forth becomes a challenge in itself. Verification teams not only struggle to manage protocol, log files and waveforms, as they additionally have to deal with functional coverage, assertion reports, code coverage, third party IP reports, offshore deliverables, mixed-language environments, and different methodologies. With constrained random verification, functional coverage report and code coverage report need to be analysed together to make more sense of them. A high percentage of functional coverage and a low percentage of code coverage is an early indication that the functional coverage plan might be incomplete. Likewise, a high percentage of code coverage report and a low percentage of functional coverage report indicate that a part of the design is not yet implemented. Verification management When carrying out verification tasks offshore, a graphical representation of the number of bugs filed and time it took to resolve these bugs helps reveal any critical bottleneck between the onsite design team and the verification team offshore. By including the progress of functional and code coverage reports in the same graph plot, one can also measure the effective progress of the stimulus and bug closure, and produce good coverage numbers. Effective tracking of the entire team’s work, both onsite and offshore, is a critical aspect of verification management. The EDA industry has started taking measures to reduce the tracking effort between what is documented, what is executed and the responsible resource. The latest EDA tools provide regression management and XML-based document templates to define the coverage plan. New-generation tools are smart enough to analyse the regression result and trace it back to the documented functional coverage plan, thus showing the overall regression run effectiveness. These tools are also able to provide analysis of individual members’ performance as they indicate the resources responsible for any particular cover point in the report. The EDA industry has likewise started standardising coverage databases used to store all the simulation data in a single database. This will ease the difficulty of report generation using different verification measurement dimensions. We are still far away from developing an effective verification management tool that will enable us to track verification progress with the issues of offshoring and the new dimensions of verification data in mind. Effective analysis and reporting of verification data at an early stage is still key to a successful verification cycle. Online Engineers demo new verification planning process Automate formal verification for Open Core Protocol EETI_mother.indd 1 1/14/08 5:17:49 PM EE Times-India | October 16-31, 2008 | www.eetindia.com http://www.eetindia.co.in/ART_8800529871_1800001_NT_9b74e2da.HTM?ClickFromNewsletter_081016 http://www.eetindia.co.in/ART_8800545328_1800000_TA_50fc7ca4.HTM?ClickFromNewsletter_081016 http://www.eetindia.co.in/STATIC/REDIRECT/Newsletter_081016_EETIreg.htm http://www.eetindia.com/STATIC/REDIRECT/Newsletter_081016_EETI02.htm?ClickFromNewsletter_081016
Table of Contents Feed for the Digital Edition of EETimes India - October 16, 2008 EETimes India - October 16, 2008 Contents National Semiconductor Tech Insights Environment Eases Reconfigurable Design, Verification Texas Instruments Digikey Grasp SystemVerilog Testbench Debug, Analysis WELCON-2008, ICQMOIT-2008, Power India 2008 EETimes India - October 16, 2008 EETimes India - October 16, 2008 - Contents (Page 1) EETimes India - October 16, 2008 - National Semiconductor (Page 2) EETimes India - October 16, 2008 - National Semiconductor (Page 3) EETimes India - October 16, 2008 - Tech Insights (Page 4) EETimes India - October 16, 2008 - Environment Eases Reconfigurable Design, Verification (Page 5) EETimes India - October 16, 2008 - Texas Instruments (Page 6) EETimes India - October 16, 2008 - Texas Instruments (Page 7) EETimes India - October 16, 2008 - Digikey (Page 8) EETimes India - October 16, 2008 - Grasp SystemVerilog Testbench Debug, Analysis (Page 9) EETimes India - October 16, 2008 - Grasp SystemVerilog Testbench Debug, Analysis (Page 10) EETimes India - October 16, 2008 - WELCON-2008, ICQMOIT-2008, Power India 2008 (Page 11)
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