EETimes India - October 16, 2008 - (Page 7)

In Focus | Verification ‘Safari’ through SoC verification continued from page vide a seamless way to manage the entire verification process. In this article, we will explore few major areas of a comprehensive verification platform. Reuse and automation The SoC era is a reality today thanks to the well-defined, time-tested Reuse Methodology Manual (RMM) published a decade ago. RMM addressed the design side issues of a SoC and touched briefly on verification aids. A similar attempt was made, quite successfully, on the verification front via the Verification Methodology Manual (VMM) published some 3 years ago. The Accellera standards organisation recently started an effort to standardise verification IP interoperability and methodology. The Accellera technical committee accepted VMM Base Classes and VMM Applications donations to address these efforts. While VIP reuse is well understood for standard interfaces, for most of the custom developed environments, reuse often happens as an afterthought. This is unintended, and is rather a result of a lack of an established set of guidelines and best practices for reusable sub-environments. A robust methodology should provide guidelines and means to create complex verification sub-environments composed of several individual verification components that can be seamlessly used across different levels of abstraction, from device modelling to hardware acceleration. Layered environment architecture with transaction level interfaces, which help decouple different components, can promote reuse in a big way and also aid in the plug and play of verification components. With a set of base classes for a methodology in place, it is the applications packages that automate more verification tasks, such as register verification, mirroring and shared memory allocation. A robust methodology should also provide built-in infrastructure support for modelling scoreboards and system per formance analyser. User testbenches can leverage the infrastructure and focus on core functionality of the system, ensuring that environmental errors are weeded out by other users and developers. Synopsys’ VCS, as an example, natively supports the industry de-facto standard VMM, and has added more automation hooks to ease creation of such environments and to perform compliance checking. VMM Applications built on top of the base classes is shown in figure 1. Management and tracking With advances in core simulator performance and leveraging standard methodology and automation, the raw “capability” of functional verification has certainly increased multi-fold. However, what is often lacking Figure 2: A sample verification project in spreadsheet view. is the ability to comprehensively measure verification progress. Just like project tracking software (such as Microsoft MPP), a more verification-aware system is needed to visualise verification progress. Such a system should be aware of various verification metrics, such as Discuss Are EDA tools hijacking creativity? Handshake CEO: Prioritise creativity over the influence of the production process to close the design productivity gap. Do you agree? Figure 1: VMM Applications built on top of proven VMM Base Classes. structural coverage, functional coverage, assertion coverage and emerging low power metrics like power state transitions (logic and voltage) coverage. Without a mature tracking system, tracking verification is like walking through a jungle with various metrics forming different trees, caves, etc. Just like a well-organised “safari” through a jungle, a verification management tool maps the verification plan to the results and shows the next steps forward. A unique requirement of a verification management system is the varied audience it caters to—ranging from system architects, project managers, team leads, and individual verification engineers. For instance, a project manager would prefer to see the various metrics corre- lated together than in isolation, while an individual verification lead may be interested in just a single feature for which he/she is responsible. Also, since management is an important consumer for such a system, it should run seamlessly on both a regular notebook PC and on a high-end UNIX server. Synopsys’ VMM Planner, for instance, provides a spreadsheet view and a core language view via a SystemVeriloglike language called Hierarchical Verification Planner (HVP). A key differentiator of VMM Planner is its open architecture in terms of ability to accept metrics from any arbitrary source. Figure 2 above shows a sample verification project being managed via VMM Planner. Conclusion With a number of recent advancements, verification is becoming the most interesting aspect of SoC design. While a brute-force, blindfolded strategy is a sure way to ensure chip re-spins guided “safari” approach--in terms of reuse, automation, verification management and multi-threaded execution--is an efficient way to keep up with the complexity of modern-day SoC verification. Software verification, debug in the MPSoC era EDA still sof t ware challenged, says analyst Online EE Times-India | October 16-31, 2008 | www.eetindia.com http://www.eetindia.co.in/STATIC/REDIRECT/Newsletter_081016_RMM.htm http://www.eetindia.co.in/STATIC/REDIRECT/Newsletter_081016_VMM.htm http://forum.eetindia.co.in/FORUM_POST_1000039193_1200077761_0.HTM?ClickFromNewsletter_081016 http://forum.eetindia.co.in/FORUM_POST_1000039193_1200077761_0.HTM?ClickFromNewsletter_081016 http://www.eetindia.co.in/ART_8800545539_1800000_TA_f41303a3.HTM?ClickFromNewsletter_081016 http://www.eetindia.co.in/ART_8800529156_1800000_NT_ce6754f1.HTM?ClickFromNewsletter_081016 http://www.eetindia.com/STATIC/REDIRECT/Newsletter_081016_EETI02.htm?ClickFromNewsletter_081016

Table of Contents Feed for the Digital Edition of EETimes India - October 16, 2008

EETimes India - October 16, 2008 Contents National Semiconductor Tech Insights Environment Eases Reconfigurable Design, Verification Texas Instruments Digikey Grasp SystemVerilog Testbench Debug, Analysis WELCON-2008, ICQMOIT-2008, Power India 2008

EETimes India - October 16, 2008

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