EETimes India - December 16, 2008 - (Page 3)

Trends Data plane processing challenges DSP By Chris Rowen Founder and CTO Tensilica, Inc. What is common to the design of a cell phone, a digital camera and a digital television? What is common to all high-volume system-on-chip (SoC) designs? When you look inside, your see the same basic elements: application processor, memory, DRAM controller, analogue interface, and data plane processing. The application processor, memory and even the analogue interface are often generic. But what makes the cell phone a phone, the camera a camera, and the digital TV a digital TV? The answer—data plane processing. The distinction between control-plane and data plane is key to understanding chip design and product differentiation. Controlplane processing includes user interfaces, system initialisation, system housekeeping, and highlevel networking protocols. Data plane processing includes the signal, image, video, audio, and data protocol processing specific to the target functions of the system. It also includes the local control of all of those functions, often weaving together the data processing of related streams, such as audio with video or wireless multimedia demodulation with multimedia decoding. Data plane processing is the heavy lifting in the application, often representing the vast majority of actual computation in the SoC. In current design scenarios, heavy data processing loads are getting heavier. Not only are wireless data rates and image resolution increasing dramatically but the target systems are increasingly becoming multistandard, multi-function, multigeography, Internet-enabled system platforms. All this complexity means that data plane processing must now be programmable. Fewer of the key functions can be satisfied with pure hardwired design in Verilog. Optimised DPUs The biggest challenge now for next-generation SoC designs is how to add programmability to the data plane. How do we Rowen: How do we make complex functions programmable to handle multiple standards, functions, geographies, and use models required in chip design? make all of these complex functions programmable to handle the multiple standards, multiple functions, multiple geographies, and multiple use models required to justify the increasing price of chip design? Yet while adding programmability, we want to make sure we use the lowest possible amount of power and get the performance of a hand-coded hardware block. The answer lies with optimised data plane processing units (DPUs), which are clusters of specialised processors matched to the target applications and used together to provide the flexible functionality at low cost and power. By using flexible memory interfaces and streaming data between data plane processors, DPUs can achieve tens of billions of operations per second and tens of gigabytes per second of bandwidth. Furthermore, these continued on page Find Datasheets Online Looking for parts to specify for your design project? Browse through thousands of datasheets organised by category, by manufacturer, and alphabetically. Search using keywords or part number to quickly access datasheets. Part No. TMS320C6701 LT1011 ADC0808 AD14060 TMS320F240 LT1635 AD9518-1 TMS320VC549 NBXSBA010 ADF4001 Description Floating-point DSP (Rev. F) Voltage comparator 8-bit microprocessor-compatible ADCs with 8-channel multiplexer 480-MFLOP, quad DSP 5V CQFP package DSP controller (Rev. E) Micropower rail-to-rail op amp and reference 6-output clock generator with integrated 2.5GHz VCO Fixed-point DSP (Rev. G) 3.3V 100MHz PureEdge LVPECL clock oscillator module 200MHz clock generator PLL Manufacturer Texas Instruments Linear Technology National Semiconductor Analog Devices Texas Instruments Linear Technology Analog Devices Texas Instruments ON Semiconductor Analog Devices Get more… 3 EE Times-India | December 16-31, 2008 | www.eetindia.com http://www.eetindia.co.in/SEARCH/SUMMARY/technical-articles/networking protocol.HTM?ClickFromNewsletter_081216 http://www.embeddeddesignindia.co.in/SEARCH/SUMMARY/technical-articles/SoC.HTM?ClickFromNewsletter_081216 http://www.eetindia.co.in/SEARCH/SUMMARY/technical-articles/%22memory interface%22.HTM?ClickFromNewsletter_081216 http://www.eetindia.co.in/SEARCH/SUMMARY/technical-articles/Verilog.HTM?ClickFromNewsletter_081216 http://www.eetindia.co.in/DATASHEET/DETAIL/TMS320C6701-1000048428.HTM?ClickFromNewsletter_081216 http://www.eetindia.co.in/DATASHEET/DETAIL/LT1011-1000041674.HTM?ClickFromNewsletter_081216 http://www.eetindia.co.in/DATASHEET/DETAIL/ADC0808-1000025033.HTM?ClickFromNewsletter_081216 http://www.eetindia.co.in/DATASHEET/DETAIL/AD14060-1000039168.HTM?ClickFromNewsletter_081216 http://www.eetindia.co.in/DATASHEET/DETAIL/TMS320F240-1000048451.HTM?ClickFromNewsletter_081216 http://www.eetindia.co.in/DATASHEET/DETAIL/LT1635-1000041975.HTM?ClickFromNewsletter_081216 http://www.eetindia.co.in/DATASHEET/DETAIL/AD9518-1-1000039976.HTM?ClickFromNewsletter_081216 http://www.eetindia.co.in/DATASHEET/DETAIL/TMS320VC549-1000048500.HTM?ClickFromNewsletter_081216 http://www.eetindia.co.in/DATASHEET/DETAIL/NBXSBA010-1000026773.HTM?ClickFromNewsletter_081216 http://www.eetindia.co.in/DATASHEET/DETAIL/ADF4001-1000040218.HTM?ClickFromNewsletter_081216 http://www.eetindia.co.in/DATASHEET/INDEX.HTM?ClickFromNewsletter_081216 http://www.eetindia.com/STATIC/REDIRECT/Newsletter_081216_EETI02.htm?ClickFromNewsletter_081216

Table of Contents Feed for the Digital Edition of EETimes India - December 16, 2008

EETimes India - December 16, 2008 Contents National Semiconductor Data Plane Processing Challenges DSP Design, Debug with DSPs TES 2008, NCMIPMV '08, ICACT '08, VLSI Conferene 2009, ICETiC 2009

EETimes India - December 16, 2008

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