EETimes India - December 16, 2008 - (Page 5)

Trends Data plane processing challenges DSP continued from page building block processors have tiny areas, and hence little power dissipation. These programmable clusters make it possible to starting planning “softwaredefined radios” or “softwaredefined video post-processing pipes” and “software-defined audio environments.” Individual DPUs are tuned to a specific task—for instance, OFDM demodulation DSP, Convolutional Turbo Code forward error correction, 7.1-channel audio stream decoding, HD 1080p video de-interlacing, scaling, or frame rate conversion. The tuning routinely makes these processors five to ten times more efficient than traditional general-purpose DSPs, so they can rival the performance of hardwired functions, but with the programming tools and off-the-shelf libraries to speed development time. Data plane processors also differ from traditional DSPs in their memory interfaces. DPU memory systems are characterised by added flexibility in the memory and cache structure, wider memory and bus interfaces, and the availability of more memory ports, which include not only traditional multi-ported “XY” memories but also superwide special memories. processing speeds come from clever architectures that bypass the bus and stream data between processors just as if those processors were blocks of hard coded logic. At these speeds, there is no reason to hard code most logic blocks any more. Just about all functions can benefit by implementing the complex bug-prone state machines in “Optimised DPUs can do the job just as fast as a dedicated hardware block, but with the benefit of being programmable and without the horrible verification cycle.” Perhaps most importantly, data plane processors employ streaming data interfaces that entirely bypass the bus to move wide data words directly between the execution units of multiple processors. The highest efficiencies and greatest data a processor for maximum flexibility and post-silicon firmware changes. Cisco uses 192 data plane processors in its high-end CRS-1 Carrier Router System. Epson uses multiple data plane-optimised processors to implement its en- tire image processing chip in its inkjet printers. Intel uses multiple high-precision DSPs to bring immersive audio experiences to its living room platforms. Wherever a lot of data needs to be processed quickly, optimised data plane processors can do the job just as fast as a dedicated hardware block, but with the benefit of being programmable and without the horrible verification cycle. RTL will always play role in SoC design, but it will fit into more narrowly specialised roles. Likewise, generic one-size-fits-all DSPs are being overshadowed by more optimised domain-oriented DPUs. Industry leaders are turning to optimised data plane processors. Are you? Online Partition multi-cores for embedded networking Real-time bandwidth, overlap processing EETI_eeNews_newsletter.indd 1 1/15/08 2:47:19 PM EE Times-India | November 16-31, 2008 | www.eetindia.com http://www.powerdesignindia.co.in/SEARCH/SUMMARY/technical-articles/DSP.HTM?ClickFromNewsletter_081216 http://www.embeddeddesignindia.co.in/ART_8800536126_2800001_TA_2f908f1e.HTM?ClickFromNewsletter_081216 http://www.embeddeddesignindia.co.in/ART_8800544382_2800002_TA_5d0fd931.HTM?ClickFromNewsletter_081216 http://www.eetindia.co.in/STATIC/REDIRECT/Newsletter_081216_EETIreg.htm http://www.eetindia.com/STATIC/REDIRECT/Newsletter_081216_EETI02.htm?ClickFromNewsletter_081216

Table of Contents Feed for the Digital Edition of EETimes India - December 16, 2008

EETimes India - December 16, 2008 Contents National Semiconductor Data Plane Processing Challenges DSP Design, Debug with DSPs TES 2008, NCMIPMV '08, ICACT '08, VLSI Conferene 2009, ICETiC 2009

EETimes India - December 16, 2008

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