EETimes India - January 1, 2009 - (Page 1)

India’s fortnightly focus on electronics design January 1-15, 2009 Hybrid solutions ease embedded devt By Frank Schirrmeister Director of Product Marketing, System-level Solutions Synopsys, Inc. Over the last couple of years, realisation has sunk in for chip development teams that software has become more important. The days when software was not part of the solution delivered by semiconductor providers are gone. Today, it often is impossible to sell silicon devices without the associated software. Software development has not only become a major part of chip development projects, but is now on the critical path for chips to go into volume production as well. This increased focus on software has already resulted in significant changes in the de- velopment chain. Intellectual property (IP) providers are either developing hardware-dependent software in house or are forming alliances with independent software providers. Semiconductor Schirrmeister: Design teams should capitalise on the combined advantages of software and hardware-based methods by using hybrid approaches. vendors have increased their investment in software development and now make software part of their delivery with the silicon. System houses are even spinning out major parts of their chip development effort in partnerships with semiconductor houses, allowing them to differentiate in software. Customers are pointing to two issues to improve software development schedules. First, software development itself must start as early as possible. Traditionally it has trailed hardware development because software development teams were waiting for hardware to become available. Second, software development productivity must increase. There are numerous ways software productivity can be improved, especially when it comes to de- velopment close to the hardwaresoftware interface. While these two principles are not causing much controversy, the different techniques to achieve them are the topic of a fair amount of debate. In their attempts to start software development early and make it more productive, design teams face a variety of options. Different vehicles can be used for software execution, namely previous generation chips, virtual platforms, hardware prototypes and the actual silicon. While the actual silicon fully represents the actual design, the other representations are available earlier in the design flow. In addition, virtual platforms and FPGA prototypes greatly increase software development productivity through continued on page Use system modelling for AMBA By Darryl Koivisto CTO Mirabilis Design, Inc. Inside Trends 2 Chip-package co-design lowers design cost Embedded system designers have a choice of using a shared or point-to-point bus in their designs. Typically, an embedded design will have a general-purpose processor, cache, SDRAM, DMA port, and Bridge port to a slower I/O bus, such as the Advanced Microcontroller Bus Architecture (AMBA) Advanced Peripheral Bus (APB). In addition, there might be a port to a DSP processor, or hardware accelerator, common with the increased use of video in many applications. As chiplevel device geometries become smaller and smaller, more and more functionality can be added without the concomitant increase in power and cost per die as seen in prior generations. System modelling is a new methodology above the detailed chip implementation level that allows one to explore different designs without having to write Verilog, System Verilog, VHDL, SystemC, or just plain C/C++ code. This saves considerable development time, and allows for more design exploration prior to selecting a design topology to begin implementation. This paper discusses the construction of an AMBA Advanced High-performance Bus (AHB) Shared Bus and AMBA Advanced eXtensible Interface (AXI) point-to-point bus using a graphical modelling environment that achieved approximately 95 per continued on page In Focus 6 7 Sub-100nm tech brings EDA opportunities Algorithmic synthesis enhances design efficiency Events 10 ICETiC 2009, IMTEX/Tooltech 2009, ISA Vision Summit 2009, COMPONEX NEPCON 2009, Convergence India 2009 Sponsors 3 National Semiconductor www.eetindia.com http://www.eetindia.co.in/SEARCH/SUMMARY/technical-articles/prototype.HTM?ClickFromNewsletter_090101 http://www.eetindia.co.in/SEARCH/SUMMARY/technical-articles/FPGA.HTM?ClickFromNewsletter_090101 http://www.eetindia.co.in/SEARCH/SUMMARY/technical-articles/bus.HTM?ClickFromNewsletter_090101 http://www.eetindia.co.in/SEARCH/SUMMARY/technical-articles/DSP.HTM?ClickFromNewsletter_090101 http://www.eetindia.com/STATIC/REDIRECT/Newsletter_090101_GS01.htm http://www.eetindia.com/STATIC/REDIRECT/Newsletter_090101_EETI02.htm

Table of Contents Feed for the Digital Edition of EETimes India - January 1, 2009

EETimes India - January 1, 2009 Contents Chip-Package Co-Design Lowers Design Cost National Semiconductor Sub-100nm Tech Brings EDA Opportunities Algorithmic Synthesis Enhances Design Efficiency ICETIC 2009, IMTEX/Tooltech 2009, ISA Vision Summit 2009, COMPONEX�NEPCON 2009, Convergence India 2009

EETimes India - January 1, 2009

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